參數(shù)資料
型號(hào)： MC92600CJUB
廠(chǎng)商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA217
封裝： 23 X 23 MM, 2.32 MM HEIGHT, 1.27 MM PITCH, PLASTIC, BGA-217
文件頁(yè)數(shù)： 43/98頁(yè)
文件大?。?/td> 1288K
代理商： MC92600CJUB
4-6
MC92600 SERDES User’s Manual
MOTOROLA
Power Supply Requirements
conguration and control signals and describes the effect of changing their state after power
up.
4.6
Power Supply Requirements
The board design should have a minimum of two solid planes of one ounce copper. One
plane is to be used as a ground plane and the second plane is to be used for the 1.8V supply.
It is recommended that the board has its own 1.8V and 3.3V regulators with less than
50 mV ripple.
4.7
Phase-Locked Loop (PLL) Power Supply Filtering
An analog power supply is required for the internal PLL. The PLLAVDD signal provides
power for the analog portions of the PLL. To ensure stability of the internal clock, the power
supplied to the PLL is ltered using a circuit similar to the one shown in Figure 4-1. For
maximum effectiveness, the lter circuit is placed as close as possible to the PLLAVDD
ball to ensure it lters out as much noise as possible. The ground connection should be near
the PLLAGND ball. The 0.01
F capacitor is closest to the ball, followed by the 1F
Table 4-4. Asynchronous Conguration and Control Signals
Signal Name
Description
Effect of Changed State
TBIE
Ten-Bit Interface Enable
Device must be reset.
HSE
Half-Speed Enable
Device must be reset.
DDRE
Double data rate enable
Device must be reset.
BSYNC_0
Word Sync. Event Method
Device must be reset.
BSYNC_1
Byte Alignment Mode
Device must be reset.
ADIE
Add/Drop Idle Enable
Device must be reset.
RCCE
Recovered Clock Enable
Device must be reset.
REPE
Repeater Mode Enable
Device must be reset.
WSE
Word Synchronization Enable
Device must be reset.
TST_0, TST_1
Test mode deners
Must be low and remain low during
normal operation
LBE
Loop Back Enable
Receiver must acquire new bit phase
alignment; byte and word
synchronization must be
re-established.
LBOE
Loopback Output Enable
Enable/disable transmit links during
testing (LBOE = high), no recovery
action necessary
STNDBY
Puts PLL Standby mode
Receiver must re-establish byte and
word synchronization.
RESET
System Reset Bar
Device is reset.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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