參數(shù)資料
型號(hào)： MC92600CJUB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA217
封裝： 23 X 23 MM, 2.32 MM HEIGHT, 1.27 MM PITCH, PLASTIC, BGA-217
文件頁(yè)數(shù)： 30/98頁(yè)
文件大?。?/td> 1288K
代理商： MC92600CJUB
3-8
MC92600 SERDES User’s Manual
MOTOROLA
Receiver Clock Timing Modes
When explicitly invalidated by asserting WSE_GEN high and XMIT_x_K low on
all four receivers.
When lock is lost, word synchronization must be re-established before data ow through
the receiver resumes.
The receiver interface is disabled during initial word alignment. No data is produced at its
outputs until word alignment is achieved and the rst non-idle character is received. When
establishing word alignment, or when word alignment is lost, the receiver’s RECV_x_ERR
signal is asserted high and the “Not Word Sync” error is reported as described in
3.3.2.2
Word Synchronization Recommended Settings
Word alignment can only be used with certain operating modes and has limited application
in others. Table 3-4 describes the relationship between modes and word synchronization.
3.4
Receiver Clock Timing Modes
The receiver interface is timed to the recovered clock or to the reference clock depending
on the state of the recovered clock enable, RCCE, signal. RCCE asserted enables timing
relative to the recovered clock, and set low enables timing relative to the reference clock.
Table 3-4. Word Synchronization Settings
Mode
Signals
Recommended
State
Description
Word synchronization
WSE
High
Enables word synchronization.
Byte synchronization
BSYNC_0,
BSYNC_1
Any mode except
non-aligned
Word synchronization depends upon idle character
detection. Byte alignment is required for idle
detection.
Add/delete idle
ADIE
High
When enabled, allows the receiver to add/delete idle
patterns to maintain word alignment. This is the
recommended operating mode when the reference
clock is being used to time the receiver interface
(RCCE = Low) and there is a frequency offset
between the transmitter and receiver. Idles are added
or dropped to maintain word alignment.
10-bit interface
TBIE
don’t care
When enabled, the idle character must be part of the
TBI code set.
When disabled, the idle is naturally supported by the
8B/10B codes.
Recovered clock
RCCE
don’t care
Does not affect word synchronization.
Half-speed enable
HSE
don’t care
Does not affect word synchronization.
Double data rate
DDRE
don’t care
Does not affect word synchronization.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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