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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� MC908LD64IFUE
寤犲晢锛� Freescale Semiconductor
鏂囦欢闋佹暩(sh霉)锛� 67/362闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MCU 8BIT FOR LCD 64-QFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 420
绯诲垪锛� HC08
鏍稿績铏曠悊鍣細 HC08
鑺珨灏哄锛� 8-浣�
閫熷害锛� 6MHz
閫i€氭€э細 I²C锛孶SB
澶栧湇瑷�(sh猫)鍌欙細 OSD锛孭OR锛孭WM
杓稿叆/杓稿嚭鏁�(sh霉)锛� 39
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绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 闁冨瓨
RAM 瀹归噺锛� 2K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 3 V ~ 3.6 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 6x8b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 64-QFP
鍖呰锛� 鎵樼洡
鐢�(ch菐n)鍝佺洰閷勯爜闈細 725 (CN2011-ZH PDF)
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Timer Interface Module (TIM)
Interrupts
MC68HC908LD64 鈥� Rev. 3.0
Data Sheet
Freescale Semiconductor
Timer Interface Module (TIM)
159
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially
control the buffered PWM output.TIM channel 0 status and control
register (TSC0) controls and monitors the PWM signal from the linked
channels.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM
overflows. Subsequent output compares try to force the output to a state
it is already in and have no effect. The result is a 0% duty cycle output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the
TOVx bit generates a 100% duty cycle output. See 11.10.4 TIM Channel
11.6 Interrupts
The following TIM sources can generate interrupt requests:
TIM overflow flag (TOF) 鈥� The TOF bit is set when the TIM
counter reaches the modulo value programmed in the TIM counter
modulo registers. The TIM overflow interrupt enable bit, TOIE,
enables TIM overflow CPU interrupt requests. TOF and TOIE are
in the TIM status and control register.
TIM channel flags (CH1F:CH0F) 鈥� The CHxF bit is set when an
input capture or output compare occurs on channel x. Channel x
TIM CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests
are enabled when CHxIE=1. CHxF and CHxIE are in the TIM
channel x status and control register.
11.7 Low-Power Modes
The WAIT and STOP instructions puts the MCU in low-power-
consumption standby modes.
11.7.1 Wait Mode
The TIM remains active after the execution of a WAIT instruction. In wait
mode the TIMA registers are not accessible by the CPU. Any enabled
CPU interrupt request from the TIM can bring the MCU out of wait mode.
If TIM functions are not required during wait mode, reduce power
consumption by stopping the TIM before executing the WAIT instruction.
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