
External Interrupt (IRQ)
IRQ Status and Control Register (INTSCR)
MC68HC908LD64 — Rev. 3.0
Data Sheet
Freescale Semiconductor
External Interrupt (IRQ)
319
20.5 IRQ Status and Control Register (INTSCR)
The IRQ status and control register (INTSCR) controls and monitors
operation of the IRQ module. The INTSCR has the following functions:
Shows the state of the IRQ flag
Clears the IRQ latch
Masks IRQ interrupt request
Controls triggering sensitivity of the IRQ interrupt pin
IRQF — IRQ Flag
This read-only status bit is high when the IRQ interrupt is pending.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a logic 1 to this write-only bit clears the IRQ latch. ACK always
reads as logic 0. Reset clears ACK.
IMASK — IRQ Interrupt Mask Bit
Writing a logic 1 to this read/write bit disables IRQ interrupt requests.
Reset clears IMASK.
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
MODE — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ pin.
Reset clears MODE.
1 = IRQ interrupt requests on falling edges and low levels
0 = IRQ interrupt requests on falling edges only
Address:
$001E
Bit 7
654321
Bit 0
Read:
0000
IRQF
0
IMASK
MODE
Write:
ACK
Reset:
00000000
= Unimplemented
Figure 20-3. IRQ Status and Control Register (INTSCR)