參數(shù)資料
型號: MC8641DVU1250JB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: MICROPROCESSOR, CBGA1023
封裝: 33 X 33 MM, ROHS COMPLIANT, CERAMIC, BGA-1023
文件頁數(shù): 62/140頁
文件大小: 1484K
代理商: MC8641DVU1250JB
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 0
28
Freescale Semiconductor
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
8
Ethernet: Enhanced Three-Speed Ethernet (eTSEC),
MII Management
This section provides the AC and DC electrical characteristics for enhanced three-speed and MII
management.
8.1
Enhanced Three-Speed Ethernet Controller (eTSEC)
(10/100/1Gb Mbps)—GMII/MII/TBI/RGMII/RTBI/RMII Electrical
Characteristics
The electrical characteristics specified here apply to all gigabit media independent interface (GMII), media
independent interface (MII), ten-bit interface (TBI), reduced gigabit media independent interface
(RGMII), reduced ten-bit interface (RTBI), and reduced media independent interface (RMII) signals
except management data input/output (MDIO) and management data clock (MDC). The RGMII and RTBI
interfaces are defined for 2.5 V, while the GMII and TBI interfaces can be operated at 3.3 or 2.5 V. Whether
the GMII or TBI interface is operated at 3.3 or 2.5 V, the timing is compliant with the IEEE 802.3 standard.
The RGMII and RTBI interfaces follow the Reduced Gigabit Media-Independent Interface (RGMII)
Specification Version 1.3 (12/10/2000). The RMII interface follows the RMII Consortium RMII
Specification Version 1.2 (3/20/1998). The electrical characteristics for MDIO and MDC are specified in
8.1.1
eTSEC DC Electrical Characteristics
All GMII, MII, TBI, RGMII, RMII and RTBI drivers and receivers comply with the DC parametric
attributes specified in Table 24 and Table 25. The potential applied to the input of a GMII, MII, TBI,
RGMII, RMII or RTBI receiver may exceed the potential of the receiver’s power supply (i.e., a GMII
driver powered from a 3.6-V supply driving VOH into a GMII receiver powered from a 2.5-V supply).
Tolerance for dissimilar GMII driver and receiver supply potentials is implicit in these specifications. The
Table 23. DUART AC Timing Specifications
Parameter
Value
Unit
Notes
Minimum baud rate
MPX clock/1,048,576
baud
1,2
Maximum baud rate
MPX clock/16
baud
1,3
Oversample rate
16
1,4
Notes:
1. Guaranteed by design.
2. MPX clock refers to the platform clock.
3. Actual attainable baud rate will be limited by the latency of interrupt processing.
4. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are
sampled each 16th sample.
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