參數(shù)資料
型號: MC8641DVU1250JB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: MICROPROCESSOR, CBGA1023
封裝: 33 X 33 MM, ROHS COMPLIANT, CERAMIC, BGA-1023
文件頁數(shù): 52/140頁
文件大?。?/td> 1484K
代理商: MC8641DVU1250JB
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
19
DDR and DDR2 SDRAM
Table 12 provides the PLL lock times.
6
DDR and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the
MPC8641. Note that DDR SDRAM is Dn_GVDD(typ) = 2.5 V and DDR2 SDRAM is
Dn_GVDD(typ) = 1.8 V.
6.1
DDR SDRAM DC Electrical Characteristics
Table 13 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the
MPC8641 when Dn_GVDD(typ) = 1.8 V.
Maximum valid-to-high impedance time for actively
driven POR configs with respect to negation of
HRESET
5
SYSCLKs
1
Notes:
1. SYSCLK is the primary clock input for the MPC8641.
2 This is related to HRESET assertion time. Stable PLL configuration inputs are required when a stable SYSCLK is
applied. See the
MPC8641D Integrated Host Processor Reference Manual for more details on the power-on reset
sequence.
Table 12. PLL Lock Times
Parameter/Condition
Min
Max
Unit
Notes
(Platform and E600) PLL lock times
100
μs1
Local bus PLL
50
μs
Notes:
1. The PLL lock time for e600 PLLs require an additional 255 MPX_CLK cycles.
Table 13. DDR2 SDRAM DC Electrical Characteristics for D
n_GVDD(typ) = 1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
I/O supply voltage
D
n_GVDD
1.71
1.89
V
1
I/O reference voltage
D
n_MVREF 0.49 × Dn_GVDD
0.51
× Dn_GVDD
V2
I/O termination voltage
VTT
D
n_MVREF –0.0
4
D
n_MVREF + 0.04
V
3
Input high voltage
VIH
D
n_MVREF+0.1
25
D
n_GVDD +0.3
V
Input low voltage
VIL
–0.3
D
n_MVREF – 0.125
V
Output leakage current
IOZ
–50
50
μA4
Table 11. RESET Initialization Timing Specifications
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