參數(shù)資料
型號(hào): MC8641DTHX1333JE
廠商: Freescale Semiconductor
文件頁數(shù): 44/130頁
文件大?。?/td> 0K
描述: IC DUAL CORE PROCESSOR 1023-CBGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC86xx
處理器類型: 32-位 MPC86xx PowerPC
速度: 1.333GHz
電壓: 1.05V
安裝類型: 表面貼裝
封裝/外殼: 1023-BCBGA,F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝: 1023-FCCBGA(33x33)
包裝: 托盤
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
20
Freescale Semiconductor
RESET Initialization
5
RESET Initialization
This section describes the AC electrical specifications for the RESET initialization timing requirements of
the MPC8641. Table 11 provides the RESET initialization AC timing specifications.
Table 12 provides the PLL lock times.
Table 11. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Notes
Required assertion time of HRESET
100
μs—
Minimum assertion time for SRESET_0 & SRESET_1
3
SYSCLKs
1
Platform PLL input setup time with stable SYSCLK
before HRESET negation
100
μs2
Input setup time for POR configs (other than PLL
config) with respect to negation of HRESET
4
SYSCLKs
1
Input hold time for all POR configs (including PLL
config) with respect to negation of HRESET
2
SYSCLKs
1
Maximum valid-to-high impedance time for actively
driven POR configs with respect to negation of
HRESET
5
SYSCLKs
1
Notes:
1. SYSCLK is the primary clock input for the MPC8641.
2 This is related to HRESET assertion time. Stable PLL configuration inputs are required when a stable SYSCLK is
applied. See the
MPC8641D Integrated Host Processor Reference Manual for more details on the power-on reset
sequence.
Table 12. PLL Lock Times
Parameter/Condition
Min
Max
Unit
Notes
(Platform and E600) PLL lock times
100
μs1
Local bus PLL
50
μs—
Note:
1.The PLL lock time for e600 PLLs require an additional 255 MPX_CLK cycles.
相關(guān)PDF資料
PDF描述
MC8641DTHX1250HE IC DUAL CORE PROCESSOR 1023-CBGA
346-020-521-201 CARDEDGE 20POS DUAL .125 GREEN
346-020-520-804 CARDEDGE 20POS DUAL .125 GREEN
346-020-520-802 CARDEDGE 20POS DUAL .125 GREEN
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