參數(shù)資料
型號: MC8641DTHX1333JE
廠商: Freescale Semiconductor
文件頁數(shù): 116/130頁
文件大?。?/td> 0K
描述: IC DUAL CORE PROCESSOR 1023-CBGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC86xx
處理器類型: 32-位 MPC86xx PowerPC
速度: 1.333GHz
電壓: 1.05V
安裝類型: 表面貼裝
封裝/外殼: 1023-BCBGA,F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝: 1023-FCCBGA(33x33)
包裝: 托盤
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
86
Freescale Semiconductor
Serial RapidIO
Figure 56. Receiver Input Compliance Mask
Table 62. Receiver Input Compliance Mask Parameters Exclusive of Sinusoidal Jitter
15.9
Measurement and Test Requirements
Since the LP-Serial electrical specification are guided by the XAUI electrical interface specified in Clause
47 of IEEE 802.3ae-2002, the measurement and test requirements defined here are similarly guided by
Clause 47. In addition, the CJPAT test pattern defined in Annex 48A of IEEE 802.3ae-2002 is specified as
the test pattern for use in eye pattern and jitter measurements. Annex 48B of IEEE 802.3ae-2002 is
recommended as a reference for additional information on jitter test methods.
15.9.1
Eye Template Measurements
For the purpose of eye template measurements, the effects of a single-pole high pass filter with a 3 dB point
at (Baud Frequency)/1667 is applied to the jitter. The data pattern for template measurements is the
Continuous Jitter Test Pattern (CJPAT) defined in Annex 48A of IEEE 802.3ae. All lanes of the LP-Serial
Receiver Type
VDIFFmin (mV)
VDIFFmax (mV)
A (UI)
B (UI)
1.25 GBaud
100
800
0.275
0.400
2.5 GBaud
100
800
0.275
0.400
3.125 GBaud
100
800
0.275
0.400
1
0
VDIFF max
-VDIFF max
VDIFF min
-VDIFF min
Time (UI)
Re
ce
iv
e
rDif
fe
re
n
tia
lI
n
p
u
tV
o
lt
a
g
e
0
AB
1-B
1-A
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MC8641DTHX1250HE IC DUAL CORE PROCESSOR 1023-CBGA
346-020-521-201 CARDEDGE 20POS DUAL .125 GREEN
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