參數(shù)資料
型號(hào)： MC8641DHX1500NC
廠商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： MICROPROCESSOR, CBGA1023
封裝： 33 X 33 MM, ROHS COMPLIANT, CERAMIC, BGA-1023
文件頁(yè)數(shù)： 120/140頁(yè)
文件大小： 1484K
代理商： MC8641DHX1500NC
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MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 0
80
Freescale Semiconductor
Serial RapidIO
15.2
AC Requirements for Serial RapidIO SD
n_REF_CLK and
SD
n_REF_CLK
Table 51 lists AC requirements.
15.3
Signal Definitions
LP-Serial links use differential signaling. This section defines terms used in the description and
specification of differential signals. Figure 53 shows how the signals are defined. The figures show
waveforms for either a transmitter output (TD and TD) or a receiver input (RD and RD). Each signal
swings between A Volts and B Volts where A > B. Using these waveforms, the definitions are as follows:
8. The transmitter output signals and the receiver input signals TD, TD, RD and RD each have a
peak-to-peak swing of A - B Volts
9. The differential output signal of the transmitter, VOD, is defined as VTD-VTD
10. The differential input signal of the receiver, VID, is defined as VRD-VRD
11. The differential output signal of the transmitter and the differential input signal of the receiver
each range from A - B to -(A - B) Volts
12. The peak value of the differential transmitter output signal and the differential receiver input
signal is A - B Volts
13. The peak-to-peak value of the differential transmitter output signal and the differential receiver
input signal is 2 * (A - B) Volts
Table 51. SD
n_REF_CLK and SDn_REF_CLK AC Requirements
Symbol
Parameter Description
Min
Typical
Max
Units
Comments
tREF
REFCLK cycle time
—
10(8)
—
ns
8 ns applies only to serial RapidIO
with 125-MHz reference clock
tREFCJ
REFCLK cycle-to-cycle jitter. Difference in the
period of any two adjacent REFCLK cycles
—
80
ps
—
tREFPJ
Phase jitter. Deviation in edge location with
respect to mean edge location
–40
—
40
ps
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