- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄3940 > MC8640VU1067NC (Freescale Semiconductor)MPU DUAL E600 994-FCCBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | MC8640VU1067NC |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 23/130頁 |
| 文件大?。?/td> | 0K |
| 描述： | MPU DUAL E600 994-FCCBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MPC86xx |
| 處理器類型： | 32-位 MPC86xx PowerPC |
| 速度： | 1.067GHz |
| 電壓： | 0.95V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 994-BCBGA，F(xiàn)CCBGA |
| 供應(yīng)商設(shè)備封裝： | 994-FCCBGA（33x33） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當(dāng)前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
119
System Design Information
Local Bus—If parity is not used, tie LDP[0:3] to ground via a 4.7-k
Ω resistor, tie LPBSE to OVDD
via a 4.7-k
Ω resistor (pull-up resistor). For systems which boot from Local Bus
(GPCM)-controlled flash, a pull-up on LGPL4 is required.
SerDes—Receiver lanes configured for PCI Express are allowed to be disconnected (as would
occur when a PCI Express slot is connected but not populated). Directions for terminating the
SerDes signals is discussed in Section 20.5.1, “Guidelines for High-Speed Interface Termination.”
20.5.1
Guidelines for High-Speed Interface Termination
This section provides the guidelines for high-speed interface termination.
20.5.1.1
SerDes Interface
The high-speed SerDes interface can be disabled through the POR input cfg_io_ports[0:3] and through the
DEVDISR register in software. If a SerDes port is disabled through the POR input the user cannot enable
it through the DEVDISR register in software. However, if a SerDes port is enabled through the POR input
the user can disable it through the DEVDISR register in software. Disabling a SerDes port through
software should be done on a temporary basis. Power is always required for the SerDes interface, even if
the port is disabled through either mechanism. Table 72 describes the possible enabled/disabled scenarios
for a SerDes port. The termination recommendations must be followed for each port.
If the high-speed SerDes port requires complete or partial termination, the unused pins should be
terminated as described in this section.
Table 72. SerDes Port Enabled/Disabled Configurations
Disabled Through POR Input
Enabled Through POR Input
Enabled through DEVDISR
SerDes port is disabled (and cannot
be enabled through DEVDISR)
Complete termination required
(Reference Clock not required)
SerDes port is enabled
Partial termination may be required1
(Reference Clock is required)
1 Partial Termination when a SerDes port is enabled through both POR input and DEVDISR is determined by the SerDes
port mode. If the port is in
×8 PCI Express mode, no termination is required because all pins are being used. If the port
is in
×1/×2/×4 PCI Express mode, termination is required on the unused pins. If the port is in ×4 serial RapidIO mode,
termination is required on the unused pins.
Disabled through DEVDISR
SerDes port is disabled (through
POR input)
Complete termination required
(Reference Clock not required)
SerDes port is disabled after software
disables port
Same termination requirements as when the
port is enabled through POR input2
(Reference Clock is required)
2 If a SerDes port is enabled through the POR input and then disabled through DEVDISR, no hardware changes are
required. Termination of the SerDes port should follow what is required when the port is enabled through both POR
input and DEVDISR. See Note 1 for more information.
Note:
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 345-012-542-804 | CARDEDGE 12POS DUAL .100 GREEN |
| 345-012-542-802 | CARDEDGE 12POS DUAL .100 GREEN |
| MC8640VU1000HC | MPU DUAL E600 994-FCCBGA |
| 345-012-542-801 | CARDEDGE 12POS DUAL .100 GREEN |
| MC8640TVU1250HC | MPU DUAL E600 994-FCCBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC8640VU1067NE | 功能描述:微處理器 - MPU G8 REV3.0 0.95V 105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC8640VU1250H | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
| MC8640VU1250HC | 功能描述:MPU DUAL E600 994-FCCBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:MPC86xx 標(biāo)準(zhǔn)包裝:1 系列:MPC85xx 處理器類型:32-位 MPC85xx PowerQUICC III 特點(diǎn):- 速度:1.2GHz 電壓:1.1V 安裝類型:表面貼裝 封裝/外殼:783-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:783-FCPBGA（29x29） 包裝:托盤 |
| MC8640VU1250N | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications Addendum for the MC8640xTxxyyyyaC Series |
| MC8641DHX1000G | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。