參數(shù)資料
型號: MC8640DVU1067NE
廠商: Freescale Semiconductor
文件頁數(shù): 90/130頁
文件大?。?/td> 0K
描述: IC MPU DUAL CORE E600 1023FCCBGA
標準包裝: 1
系列: MPC86xx
處理器類型: 32-位 MPC86xx PowerPC
速度: 1.067GHz
電壓: 0.95V
安裝類型: 表面貼裝
封裝/外殼: 1023-BCBGA,F(xiàn)CCBGA
供應商設備封裝: 1023-FCCBGA(33x33)
包裝: 托盤
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
62
Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
Figure 41. Differential Reference Clock Input DC Requirements (External AC-Coupled)
Figure 42. Single-Ended Reference Clock Input DC Requirements
13.2.3
Interfacing With Other Differential Signaling Levels
The following list explains characteristics of interfacing with other differential signaling levels.
With on-chip termination to SGND, the differential reference clocks inputs are HCSL (high-speed
current steering logic) compatible DC-coupled.
Many other low voltage differential type outputs like LVDS (low voltage differential signaling) can
be used but may need to be AC-coupled due to the limited common mode input range allowed (100
to 400 mV) for DC-coupled connection.
LVPECL outputs can produce signal with too large amplitude. It may need to be DC-biased at
clock driver output first and followed with series attenuation resistor to reduce the amplitude, in
addition to AC-coupling.
SD
n_REF_CLK
SD
n_REF_CLK
Vcm
200mV < Input Amplitude or Differential Peak < 800mV
Vmax < Vcm + 400 mV
Vmin > Vcm – 400 mV
SD
n_REF_CLK
SD
n_REF_CLK
400 mV < SD
n_REF_CLK Input Amplitude < 800 mV
0V
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