參數(shù)資料
型號： MC8640DVU1067NE
廠商： Freescale Semiconductor
文件頁數(shù)： 111/130頁
文件大小： 0K
描述： IC MPU DUAL CORE E600 1023FCCBGA
標(biāo)準(zhǔn)包裝： 1
系列： MPC86xx
處理器類型： 32-位 MPC86xx PowerPC
速度： 1.067GHz
電壓： 0.95V
安裝類型： 表面貼裝
封裝/外殼： 1023-BCBGA，F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝： 1023-FCCBGA（33x33）
包裝： 托盤
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
81
Serial RapidIO
inter-symbol interference) need only comply with the transmitter output compliance mask when
pre-emphasis is disabled or minimized.
Figure 54. Transmitter Output Compliance Mask
Table 58 specifies the parameters for the transmitter differential output eye diagram.
15.7
Receiver Specifications
LP-Serial receiver electrical and timing specifications are stated in the text and Table 59 through Table 61.
Receiver input impedance shall result in a differential return loss better that 10 dB and a common mode
return loss better than 6 dB from 100 MHz to (0.8)
× (Baud Frequency). This includes contributions from
on-chip circuitry, the chip package and any off-chip components related to the receiver. AC-coupling
Table 58. Transmitter Differential Output Eye Diagram Parameters
Transmitter Type
VDIFFmin (mV)
VDIFFmax (mV)
A (UI)
B (UI)
1.25 GBaud short range
250
500
0.175
0.39
1.25 GBaud long range
400
800
0.175
0.39
2.5 GBaud short range
250
500
0.175
0.39
2.5 GBaud long range
400
800
0.175
0.39
3.125 GBaud short range
250
500
0.175
0.39
3.125 GBaud long range
400
800
0.175
0.39
0
VDIFF min
VDIFF max
–VDIFF min
–
VDIFF max
0B
1-B
1
Time in UI
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