參數(shù)資料
型號(hào)： MC8640DVU1067NE
廠商： Freescale Semiconductor
文件頁數(shù)： 21/130頁
文件大小： 0K
描述： IC MPU DUAL CORE E600 1023FCCBGA
標(biāo)準(zhǔn)包裝： 1
系列： MPC86xx
處理器類型： 32-位 MPC86xx PowerPC
速度： 1.067GHz
電壓： 0.95V
安裝類型： 表面貼裝
封裝/外殼： 1023-BCBGA，F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝： 1023-FCCBGA（33x33）
包裝： 托盤
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
117
System Design Information
Figure 64. MPC8640 PLL Power Supply Filter Circuit (for cores)
The AVDD_SRDSn signals provide power for the analog portions of the SerDes PLL. To ensure stability
of the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in
following figure. For maximum effectiveness, the filter circuit is placed as closely as possible to the
AVDD_SRDSn balls to ensure it filters out as much noise as possible. The ground connection should be
near the AVDD_SRDSn balls. The 0.003-F capacitor is closest to the balls, followed by the two 2.2-F
capacitors, and finally the 1-
Ω resistor to the board supply plane. The capacitors are connected from
AVDD_SRDSn to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant
frequency. All traces should be kept short, wide, and direct.
Figure 65. SerDes PLL Power Supply Filter
Note the following:
AVDD_SRDSn should be a filtered version of SVDD.
Signals on the SerDes interface are fed from the SVDD power plan.
20.2.2
PLL Power Supply Sequencing
For details on power sequencing for the AVDD type and supplies refer to Section 2.2, “Power-Up/Down
20.3
Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the device can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the MPC8640 system, and the device
itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system
VDD_Core0/1
AVDD_Core0/1
2.2 F
GND
Low ESL Surface Mount Capacitors
10
Ω
Filter Circuit (should not be used for Single core device)
Note: For single core device the filter circuit (in the dashed box) should
be removed and AVDD_Core1 should be tied to ground with a weak
(2–10 k
Ω) pull-down resistor.
2.2 F 1
0.003 F
GND
1.0
Ω
AVDD_SRDSn
1. An 0805 sized capacitor is recommended for system initial bring-up.
SVDD
2.2 F 1
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