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參數(shù)資料
| 型號： | MC80F0224Q |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁數(shù)： | 94/128頁 |
| 文件大?。?/td> | 1408K |
| 代理商： | MC80F0224Q |
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MC80F0208/16/24
Preliminary
90
MAR. 2005 Ver 0.2
General-purpose register save/restore using push and pop instruc-
tions;
19.2 BRK Interrupt
Software interrupt can be invoked by BRK instruction, which has
the lowest priority order.
Interrupt vector address of BRK is shared with the vector of
TCALL 0 (Refer to Program Memory Section). When BRK inter-
rupt is generated, B-flag of PSW is set to distinguish BRK from
TCALL 0.
Each processing step is determined by B-flag as shown in Figure
19-5.
Figure 19-5 Execution of BRK/TCALL0
19.3 Shared Interrupt Vector
In case of using interrupts of Watchdog Timer and Watch Timer
together, it is necessary to check IFR in interrupt service routine
to find out which interrupt is occurred, because the Watchdog
timer and Watch timer is shared with interrupt vector address.
These flag bits must be cleared by software after reading this reg-
ister.
In case of using interrupts of UART0 Tx and UART0 Rx togeth-
er, it is necessary to check IFR in interrupt service routine to find
out which interrupt is occurred, because the UART0 Tx and
UART0 Rx is shared with interrupt vector address. These flag
bits must be cleared by software after reading this register.
In case of using interrupts of UART1 Tx and UART1 Rx togeth-
er, it is necessary to check IFR in interrupt service routine to find
out which interrupt is occurred, because the UART1 Tx and
UART1 Rx is shared with interrupt vector address. These flag
bits must be cleared by software after reading this register. Each
interrupt processing
POP
POP
POP
RETI
Y
X
A
;RESTORE Y REG.
;RESTORE X REG.
;RESTORE ACC.
;RETURN
main task
interrupt
service task
saving
registers
restoring
registers
acceptance of
interrupt
interrupt return
B-FLAG
BRK
INTERRUPT
ROUTINE
RETI
TCALL0
ROUTINE
RET
BRK or
TCALL0
=0
=1
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