MC80F0208/16/24
Preliminary
46
MAR. 2005 Ver 0.2
13. WATCH TIMER
The watch timer generates interrupt for watch operation. The
watch timer consists of the clock selector, 15-bit binary counter,
interval selector and watch timer mode register. It is a multi-pur-
pose timer. It is generally used for watch design.
The bit 0,1 of WTMR select the clock source of watch timer
among f
XIN
÷
2, f
XIN
÷
2
7
and main-clock(f
XIN
). The f
XIN
of main-
clock is used usually for watch timer test, so generally it is not
used for the clock source of watch timer. The f
XIN
÷
2
7
of main-
clock(4.194MHz) is used when the single clock system is orga-
nized. In f
XIN
÷
2
7
clock source, if the CPU enters into stop mode,
the main-clock is stopped and then watch timer is also stopped.
The watch timer counter can output with period of max 1 seconds
at sub-clock. The bit 2, 3, 4 of WTMR select the interrupt interval
divide ratio selection of watch timer among 16, 64, 256, 1024,
4096, 8192, 16384 or 32768.
The WTIF bit of IFR register is set when watch timer interrupt is
generated. (Refer to Figure 12-4)
Figure 13-1 Watch Timer Mode Register
Figure 13-2 Watch Timer Block Diagram
7 6 5 4 3 2 1 0
-
WTEN
WTIN2
-
INITIAL VALUE:0--0 0000
B
ADDRESS: 0F6
H
WTMR (Watch Timer Mode Register)
R/W
R/W
R/W
R/W
R/W
WTEN (Watch Timer Enable)
0: Watch Timer disable
1: Watch Timer Enable
Watch Timer Interrupt Interval selection
000: Clock Source
÷
32768
001: Clock Source
÷
16384
010: Clock Source
÷
8192
011: Clock Source
÷
4096
100: Clock Source
÷
1024
101: Clock Source
÷
256
110: Clock Source
÷
64
111: Clock Source
÷
16
W
Watch Timer Clock Source selection
00: -
01: f
XIN
÷
128
10: f
XIN
11: f
XIN
÷
2
WTCK1
WTCK0
WTIN1
WTIN0
MUX
f
XIN
f
XIN
÷
2
f
XIN
÷
128
WTCK[1:0]
WTIN[2:0]
WTEN
Watch Timer interrupt
MUX
÷
1024
÷
256
÷
64
÷
16
1
÷
32768
÷
16384
÷
8192
÷
4096
interval
selector
Clock Source
Selector
Clear
If WTEN=0
01
10
11