
16
ATtiny28L/V
1062F–AVR–07/06
Note:
1. Due to limited number of clock cycles in the start-up period, it is recommended that
ceramic resonator be used.
This table shows the start-up times from reset. From Power-down mode, only the clock
counting part of the start-up time is used. The Watchdog oscillator is used for timing the
real-time part of the start-up time. The number WDT oscillator cycles used for each
The frequency of the Watchdog oscillator is voltage-dependent, as shown in the section
The device is shipped with CKSEL = 0010.
Power-on Reset
A Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The detec-
tion level is nominally 1.4V. The POR is activated whenever V
CC is below the detection
level. The POR circuit can be used to trigger the start-up reset, as well as detect a fail-
ure in supply voltage.
The Power-on Reset (POR) circuit ensures that the device is reset from power-on.
Reaching the Power-on Reset threshold voltage invokes a delay counter, which deter-
mines the delay for which the device is kept in RESET after V
CC rise. The time-out
period of the delay counter can be defined by the user through the CKSEL fuses. The
different selections for the delay period are presented in
Table 5. The RESET signal is
Table 5. ATtiny28 Clock Options and Start-up Time
CKSEL3..0
Clock Source
Start-up Time at 2.7V
1111
External Crystal/Ceramic Resonator
(1)1K CK
1110
External Crystal/Ceramic Resonator
(1)4.2 ms + 1K CK
1101
External Crystal/Ceramic Resonator
(1)67 ms + 1K CK
1100
External Crystal/Ceramic Resonator
16K CK
1011
External Crystal/Ceramic Resonator
4.2 ms + 16K CK
1010
External Crystal/Ceramic Resonator
67 ms + 16K CK
1001
External Low-frequency Crystal
67 ms + 1K CK
1000
External Low-frequency Crystal
67 ms + 32K CK
0111
External RC Oscillator
6 CK
0110
External RC Oscillator
4.2 ms + 6 CK
0101
External RC Oscillator
67 ms + 6 CK
0100
Internal RC Oscillator
6 CK
0011
Internal RC Oscillator
4.2 ms + 6 CK
0010
Internal RC Oscillator
67 ms + 6 CK
0001
External Clock
6 CK
0000
External Clock
4.2 ms + 6 CK
Table 6. Number of Watchdog Oscillator Cycles
Time-out
Number of Cycles
4.2 ms
1K
67 ms
16K