參數(shù)資料
型號(hào)： MC80C52CXXX-30P883
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 30 MHz, MICROCONTROLLER, CDIP40
文件頁數(shù)： 15/81頁
文件大?。?/td> 663K
代理商： MC80C52CXXX-30P883
22
ATtiny28L/V
1062F–AVR–07/06
Register Description
Interrupt Control Register –
ICR
Bit 7 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and I-bit in the Status Register (SREG) is set (one), the
external pin interrupt 1 is enabled. The interrupt Sense Control1 bits 1/0 (ISC11 and
ISC10) define whether the external interrupt is activated on rising or falling edge, on pin
change or low level of the INT1 pin. The corresponding interrupt of External Interrupt
Request 1 is executed from program memory address $002. See also “External
Interrupt”.
Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt 0 is enabled. The interrupt Sense Control0 bits 1/0 (ISC01 and
ISC00) define whether the external interrupt is activated on rising or falling edge, on pin
change or low level of the INT0 pin. The corresponding interrupt of External Interrupt
Request 0 is executed from program memory address $001. See also “External
Interrupt”.
Bit 5 – LLIE: Low-level Input Interrupt Enable
When the LLIE is set (one) and the I-bit in the status register (SREG) is set (one), the
interrupt on low-level input is activated. Any of the Port B pins pulled low will then cause
an interrupt. However, if any Port B pins are used for other special features, these pins
will not trigger the interrupt. The corresponding interrupt of Low-level Input Interrupt
Request is executed from program memory address $003. See also “Low-level Input
Interrupt”.
Bit 4 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow Interrupt is enabled. The corresponding interrupt (at vector
$004) is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set
in the Interrupt Flag Register (IFR).
Bits 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the
corresponding interrupt enable are set. The level and edges on the external INT1 pin
that activate the interrupt are defined in Table 8.
Bit
7
654
3210
$06
INT1
INT0
LLIE
TOIE0
ISC11
ISC10
ISC01
ISC00
ICR
Read/Write
R/W
Initial Value
0
000
0000
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