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參數(shù)資料
| 型號： | MC80C0216Q |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁數(shù)： | 90/128頁 |
| 文件大?。?/td> | 1408K |
| 代理商： | MC80C0216Q |
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MC80F0208/16/24
Preliminary
86
MAR. 2005 Ver 0.2
19. INTERRUPTS
The MC80F0208/16/24 interrupt circuits consist of Interrupt en-
able register (IENH, IENL), Interrupt request flags of IRQH,
IRQL, Priority circuit, and Master enable flag (“I” flag of PSW).
Fifteen interrupt sources are provided. The configuration of inter-
rupt circuit is shown in Figure 19-1 and interrupt priority is
shown in Table 19-1.
The External Interrupts INT0 ~ INT3 each can be transition-acti-
vated (1-to-0 or 0-to-1 transition) by selection IEDS register.
The flags that actually generate these interrupts are bit INT0IF,
INT1IF, INT2IF and INT3IF in register IRQH. When an external
interrupt is generated, the generated flag is cleared by the hard-
ware when the service routine is vectored to only if the interrupt
was transition-activated.
The Timer 0 ~ Timer 4 Interrupts are generated by T0IF, T1IF,
T2IF, T3IF and T4IF which is set by a match in their respective
timer/counter register.
The Basic Interval Timer Interrupt is generated by BITIF which
is set by an overflow in the timer register.
The AD converter Interrupt is generated by ADCIF which is set
by finishing the analog to digital conversion.
The Watchdog timer and Watch Timer Interrupt is generated by
WDTIF and WTIF which is set by a match in Watchdog timer
register or Watch timer register. The IFR(Interrupt Flag Register)
is used for discrimination of the interrupt source among these two
Watchdog timer and Watch Timer Interrupt.
Figure 19-1 Block Diagram of Interrupt
UART0 Tx/Rx
INT2
INT1
INT0
INT0IF
IENH
Interrupt Enable
Register (Higher byte)
Interrupt Enable
Register (Lower byte)
IRQH
[0EC
H
]
IRQL
[0ED
H
]
Internal bus line
Internal bus line
Release STOP/SLEEP
To CPU
Interrupt Master
Enable Flag
I-flag
IENL
P
I-flag is in PSW, it is cleared by “DI”, set by
“EI” instruction. When it goes interrupt service,
I-flag is cleared by hardware, thus any other
interrupt are inhibited. When interrupt service is
completed by “RETI” instruction, I-flag is set to
“1” by hardware.
[0EA
H
]
INT1IF
INT2IF
INT3IF
UART0IF
T0IF
SIOIF
INT3
UART1 Tx/Rx
Timer 0
Serial
UART1IF
Timer 1
T1IF
T4IF
T3IF
Timer 2
Timer 3
Timer 3
T2IF
A/D Converter
ADCIF
BITIF
WTIF
Watchdog Timer
BIT
Watch Timer
WDTIF
[0EB
H
]
Communication
Interrupt
Vector
Address
Generator
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