參數(shù)資料
型號(hào)： MC80C0216Q
廠商： Electronic Theatre Controls, Inc.
元件分類： 8位微控制器
英文描述： 8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 8位單晶片微控制器
文件頁(yè)數(shù)： 77/128頁(yè)
文件大?。?/td> 1408K
代理商： MC80C0216Q
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Preliminary
MC80F0208/16/24
MAR. 2005 Ver 0.2
73
Serial I/O Mode Register(SIOM) controls serial I/O function. Ac-
cording to SCK1 and SCK0, the internal clock or external clock
can be selected.
Serial I/O Data Register(SIOR) is an 8-bit shift register. First
LSB is send or is received.
Figure 16-2 SIO Control Register
16.1 Transmission/Receiving Timing
The serial transmission is started by setting SIOST(bit1 of SIOM)
to “1”. After one cycle of SCK, SIOST is cleared automatically
to “0”. At the default state of POL bit clear, the serial output data
from 8-bit shift register is output at falling edge of SCLK, and in-
put data is latched at rising edge of SCLK pin (Refer to Figure 16-
3). When transmission clock is counted 8 times, serial I/O counter
is cleared as ‘0”. Transmission clock is halted in “H” state and se-
rial I/O interrupt(SIOIF) occurred.
BTCL
7
6
5
4
3
2
1
0
IOSW
POL
SIOST
Serial transmission status bit
0: Serial transmission is in progress
1: Serial transmission is completed
Serial transmission Clock selection
00: f
XIN
÷
4
01: f
XIN
÷
16
10: TMR0OV(Timer0 Overflow)
11: External Clock
INITIAL VALUE: 0000 0001
B
ADDRESS: 0E2
H
SIOM
SIOSF
Serial Input Pin Selection bit
0: SI Pin Selection
1: SO Pin Selection
R/W
R/W
R/W
R/W
R/W
R
Serial transmission start bit
Setting this bit starts an Serial transmission.
After one cycle, bit is cleared to “0” by hardware.
SM1
SM0
R/W
Serial transmission Operation Mode
00: Normal Port(R42,R43,R44)
01: Sending Mode(SCK,R43,SO)
10: Receiving Mode(SCK,SI,R44)
11: Sending & Receiving Mode(SCK,SI,SO)
INITIAL VALUE: Undefined
ADDRESS: 0E3
SIOR
BTCL
7
6
5
4
3
2
1
0
R/W R/W R/W R/W
R/W R/W
R/W
R/W
Sending Data at Sending Mode
Receiving Data at Receiving Mode
Serial Clock Polarity Selection bit
0: Data Transmission at Falling Edge
Received Data Latch at Rising Edge
1: Data Transmission at Rising Edge
Received Data Latch at Falling Edge
R/W
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