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| 型號： | MC7457VG867NC |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 17/71頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU RISC 867MHZ 483FCCBGA |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | MPC74xx |
| 處理器類型： | 32-位 MPC74xx PowerPC |
| 速度： | 867MHz |
| 電壓： | 1.1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 483-BCBGA，F(xiàn)CCBGA |
| 供應(yīng)商設(shè)備封裝： | 483-FCCBGA（29x29） |
| 包裝： | 托盤 |
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MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8
Electrical and Thermal Characteristics
Freescale Semiconductor
24
5.2.4
L3 Bus AC Specifications
The MPC7457 L3 interface supports three different types of SRAM: source-synchronous, double data rate
(DDR) MSUG2 SRAM, Late Write SRAMs, and pipeline burst (PB2) SRAMs. Each requires a different
protocol on the L3 interface and a different routing of the L3 clock signals. The type of SRAM is
programmed in L3CR[22:23] and the MPC7457 then follows the appropriate protocol for that type. The
designer must connect and route the L3 signals appropriately for each type of SRAM. Following are some
observations about the L3 interface.
The routing for the point-to-point signals (L3_CLK[0:1], L3DATA[0:63], L3DP[0:7], and
L3_ECHO_CLK[0:3]) to a particular SRAM must be delay matched.
For 1-Mbyte of SRAM, use L3_ADDR[16:0] (L3_ADDR[0] is LSB)
For 2-Mbyte of SRAM, use L3_ADDR[17:0] (L3_ADDR[0] is LSB)
For 4-Mbyte of SRAM, use L3_ADDR[18:0] (L3_ADDR[0] is LSB)
No pull-up resistors are required for the L3 interface
For high-speed operations, L3 interface address and control signals should be a ‘T’ with minimal
stubs to the two loads; data and clock signals should be point-to-point to their single load. Figure 8
shows the AC test load for the L3 interface.
Figure 8. AC Test Load for the L3 Interface
In general, if routing is short, delay-matched, and designed for incident wave reception and minimal
reflection, there is a high probability that the AC timing of the MPC7457 L3 interface will meet the
maximum frequency operation of appropriately chosen SRAMs. This is despite the pessimistic,
guard-banded AC specifications (see Table 12, Table 13, and Table 14), the limitations of functional
testers described in Section 5.2.3, “L3 Clock AC Specifications,” and the uncertainty of clocks and signals
which inevitably make worst-case critical path timing analysis pessimistic.
More specifically, certain signals within groups should be delay-matched with others in the same group
while intergroup routing is less critical. Only the address and control signals are common to both SRAMs
and additional timing margin is available for these signals. The double-clocked data signals are grouped
with individual clocks as shown in Figure 9 or Figure 11, depending on the type of SRAM. For example,
for the MSUG2 DDR SRAM (see Figure 9); L3DATA[0:31], L3DP[0:3], and L3_CLK[0] form a closely
coupled group of outputs from the MPC7457; while L3DATA[0:15], L3DP[0:1], and L3_ECHO_CLK[0]
form a closely coupled group of inputs.
The MPC7450 RISC Microprocessor Family User’s Manual refers to logical settings called ‘sample
points’ used in the synchronization of reads from the receive FIFO. The computation of the correct value
for this setting is system-dependent and is described in the MPC7450 RISC Microprocessor Family User’s
Manual. Three specifications are used in this calculation and are given in Table 11. It is essential that all
three specifications are included in the calculations to determine the sample points, as incorrect settings
can result in errors and unpredictable behavior. For more information, see the MPC7450 RISC
Microprocessor Family User’s Manual.
Output
Z0 = 50 Ω
GVDD/2
RL = 50 Ω
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