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參數(shù)資料
| 型號： | MC7457VG733NC |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 733 MHz, RISC PROCESSOR, CBGA483 |
| 封裝： | 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM PITCH, ROHS COMPLIANT, CERAMIC, BGA-483 |
| 文件頁數(shù)： | 3/73頁 |
| 文件大?。?/td> | 1715K |
| 代理商： | MC7457VG733NC |
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MPC7457 RISC Microprocessor Hardware Specifications, Rev. 7
Freescale Semiconductor
11
Electrical and Thermal Characteristics
Figure 2 shows the undershoot and overshoot voltage on the MPC7457.
Table 2. Absolute Maximum Ratings 1
Characteristic
Symbol
Maximum Value
Unit
Notes
Core supply voltage
VDD
–0.3 to 1.60
V
2
PLL supply voltage
AVDD
–0.3 to 1.60
V
2
Processor bus supply voltage
BVSEL = 0
OVDD
–0.3 to 1.95
V
3, 4
BVSEL = HRESET or OVDD
OVDD
–0.3 to 2.7
V
3, 5
L3 bus supply voltage
L3VSEL = HRESET
GVDD
–0.3 to 1.65
V
3, 6
L3VSEL = 0
GVDD
–0.3 to 1.95
V
3, 7
L3VSEL = HRESET or GVDD
GVDD
–0.3 to 2.7
V
3, 8
Input voltage
Processor bus
Vin
–0.3 to OVDD + 0.3
V
9, 10
L3 bus
Vin
–0.3 to GVDD + 0.3
V
9, 10
JTAG signals
Vin
–0.3 to OVDD + 0.3
V
Storage temperature range
Tstg
–55 to 150
°C
Notes:
1. Functional and tested operating conditions are given in Table 4. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. Caution: VDD/AVDD must not exceed OVDD/GVDD by more than 1.0 V during normal operation; this limit may be exceeded
for a maximum of 20 ms during power-on reset and power-down sequences.
3. Caution: OVDD/GVDD must not exceed VDD/AVDD by more than 2.0 V during normal operation; this limit may be exceeded
for a maximum of 20 ms during power-on reset and power-down sequences.
4. BVSEL must be set to 0, such that the bus is in 1.8-V mode.
5. BVSEL must be set to HRESET or 1, such that the bus is in 2.5-V mode.
6. L3VSEL must be set to HRESET (inverse of HRESET), such that the bus is in 1.5-V mode.
7. L3VSEL must be set to 0, such that the bus is in 1.8-V mode.
8. L3VSEL must be set to HRESET or 1, such that the bus is in 2.5-V mode.
9. Caution: Vin must not exceed OVDD or GVDD by more than 0.3 V at any time including during power-on reset.
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