參數(shù)資料
型號： MC7457RX1000NC
廠商： Freescale Semiconductor
文件頁數(shù)： 9/71頁
文件大小： 0K
描述： IC MPU RISC 32BIT 483FCCBGA
標(biāo)準(zhǔn)包裝： 36
系列： MPC74xx
處理器類型： 32-位 MPC74xx PowerPC
速度： 1.0GHz
電壓： 1.1V
安裝類型： 表面貼裝
封裝/外殼： 483-BCBGA，F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝： 483-FCCBGA（29x29）
包裝： 托盤
Electrical and Thermal Characteristics
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8
Freescale Semiconductor
17
5.2
AC Electrical Characteristics
This section provides the AC electrical characteristics for the MPC7457. After fabrication, functional parts
are sorted by maximum processor core frequency as shown in Section 1.5.2.1, “Clock AC Specifications,”
and tested for conformance to the AC specifications for that frequency. The processor core frequency is
determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0:4] signals. Parts are sold
by maximum processor core frequency; see Section 1.11, “Ordering Information.”
5.2.1
Clock AC Specifications
Table 8 provides the clock AC timing specifications as defined in Figure 6 and represents the tested
operating frequencies of the devices. The maximum system bus frequency, fSYSCLK, given in Table 8 is
considered a practical maximum in a typical single-processor system. The actual maximum SYSCLK
frequency for any application of the MPC7457 will be a function of the AC timings of the MPC7457, the
AC timings for the system controller, bus loading, printed-circuit board topology, trace lengths, and so
forth, and may be less than the value given in Table 8. For information regarding the use of spread
Sources.” PLL configuration and bus-to-core multiplier information is found in Section 9.1.1, “Core
Table 8. Clock AC Timing Specifications
At recommended operating conditions. See Table 4.
Characteristic
Symbol
Maximum Processor Core Frequency
Unit
Notes
867 MHz
1000 MHz
1200 MHz
1267 MHz
Min
Max
Min
Max
Min
Max
Min
Max
Processor frequency
fcore
600
867
600
1000
600
1200
600
1267
MHz
1
VCO frequency
fVCO
1200
1733
1200
2000
1200
2400
1200
2534
MHz
1
SYSCLK frequency
fSYSCLK
33
167
33
167
33
167
33
167
MHz
1, 2
SYSCLK cycle time
tSYSCLK
6.0
30
6.0
30
6.0
30
6.0
30
ns
2
SYSCLK rise and fall time
tKR, tKF
—1.0
ns
3
SYSCLK duty cycle measured
at OVDD/2
tKHKL/
tSYSCLK
40
60
40
60
40
60
40
60
%
4
SYSCLK cycle-to-cycle jitter
—
150
—
150
—
150
—
150
ps
5, 6
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