參數(shù)資料
型號(hào)： MC7455ARX867LG
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 867 MHz, RISC PROCESSOR, CBGA483
封裝： 29 X 29 MM, 1.27 MM PITCH, CERAMIC, BGA-483
文件頁數(shù)： 16/76頁
文件大?。?/td> 1520K
代理商： MC7455ARX867LG
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receive FIFO. This clock is asynchronous to all other processor clocks. This latched data is subsequently read out of the FIFO synchronously to the
processor clock. The time between writing and reading the data is set by the using the sample point settings defined in the L3CR register.
Table 12 provides the L3 bus interface AC timing specifications for the configuration as shown in Figure 9, assuming the timing relationships shown
in Figure 10 and the loading shown in Figure 8.
Table 12. L3 Bus Interface AC Timing Specifications for MSUG2
At recommended operating conditions. See Table 4.
Parameter
Symbol
All Speed Grades 8
Unit
Notes
L3OH0 = 0, L3OH1 = 0
L3OH0 = 0, L3OH1 =1
L3OH0 = 1, L3OH1 = 0
L3OH0 = 1, L3OH1 = 1
Min
Max
Min
Max
Min
Max
Min
Max
L3_CLK rise and fall time
tL3CR,
tL3CF
—1.0
ns
1
Setup times: Data and parity
tL3DVEH,
tL3DVEL
– 0.1
—
– 0.1
—
– 0.1
—
– 0.1
—
ns
2, 3,
4
Input hold times: Data and
parity
tL3DXEH,
tL3DXEL
tL3_CLK/4
+ 0.30
—tL3_CLK/4
+ 0.30
—tL3_CLK/4
+ 0.30
—tL3_CLK/4
+ 0.30
—ns
2, 4
Valid times: Data and parity
tL3CHDV,
tL3CLDV
—(– tL3_CLK/4)
+ 0.60
—(– tL3_CLK/4)
+ 0.40
—(– tL3_CLK/4)
+ 0.20
—(– tL3_CLK/4)
+ 0.00
ns
5, 6,
7
Valid times: All other outputs
tL3CHOV
—tL3_CLK/4
+ 0.80
—tL3_CLK/4
+ 0.60
—tL3_CLK/4
+ 0.40
—tL3_CLK/4
+ 0.20
ns
5, 7
Output hold times: Data and
parity
tL3CHDX,
tL3CLDX,
tL3_CLK/4
– 0.40
—tL3_CLK/4
– 0.60
—tL3_CLK/4
– 0.80
—tL3_CLK/4
– 1.00
—ns
5, 6,
7
Output hold times: All other
outputs
tL3CHOX
tL3_CLK/4
– 0.20
—tL3_CLK/4
– 0.40
—tL3_CLK/4
– 0.60
—tL3_CLK/4
– 0.80
—ns
5, 7
L3_CLK to high impedance:
Data and parity
tL3CLDZ
—tL3_CLK/2
—
tL3_CLK/2
—
tL3_CLK/2
—
tL3_CLK/2
ns
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