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參數(shù)資料
| 型號： | MC7455ARX733LF |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 733 MHz, RISC PROCESSOR, CBGA483 |
| 封裝： | 29 X 29 MM, 1.27 MM PITCH, CERAMIC, BGA-483 |
| 文件頁數(shù)： | 47/68頁 |
| 文件大?。?/td> | 1609K |
| 代理商： | MC7455ARX733LF |
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MOTOROLA
MPC7455 RISC Microprocessor Hardware Specifications
51
System Design Information
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the VDD, GVDD, and OVDD planes, to enable quick recharging of the smaller chip capacitors. These
bulk capacitors should have a low equivalent series resistance (ESR) rating to ensure the quick response
time necessary. They should also be connected to the power and ground planes through two vias to minimize
inductance. Suggested bulk capacitors: 100–330 F (AVX TPS tantalum or Sanyo OSCON).
1.9.4
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to OVDD. Unused active high inputs should be connected to
GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external VDD, OVDD, GVDD, and GND pins in the
MPC7455. If the L3 interface is not used, GVDD should be connected to the OVDD power plane, and
L3VSEL should be connected to BVSEL.
1.9.5
Output Buffer DC Impedance
The MPC7455 processor bus and L3 I/O drivers are characterized over process, voltage, and temperature.
To measure Z0, an external resistor is connected from the chip pad to OVDD or GND. Then, the value of
each resistor is varied until the pad voltage is OVDD/2 (see Figure 23).
The output impedance is the average of two components, the resistances of the pull-up and pull-down
devices. When data is held low, SW2 is closed (SW1 is open), and RN is trimmed until the voltage at the
pad equals OVDD/2. RN then becomes the resistance of the pull-down devices. When data is held high, SW1
is closed (SW2 is open), and RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes
the resistance of the pull-up devices. RP and RN are designed to be close to each other in value. Then, Z0 =
(RP + RN)/2.
Figure 25. Driver Impedance Measurement
Table 19 summarizes the signal impedance results. The impedance increases with junction temperature and
is relatively unaffected by bus voltage.
OVDD
OGND
RP
RN
Pad
Data
SW1
SW2
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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