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參數(shù)資料
| 型號： | MC7455ARX733LF |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 733 MHz, RISC PROCESSOR, CBGA483 |
| 封裝： | 29 X 29 MM, 1.27 MM PITCH, CERAMIC, BGA-483 |
| 文件頁數(shù)： | 10/68頁 |
| 文件大?。?/td> | 1609K |
| 代理商： | MC7455ARX733LF |
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18
MPC7455 RISC Microprocessor Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
Figure 4 provides the AC test load for the MPC7455.
Figure 4. AC Test Load
SYSCLK to ARTRY/SHD0/SHD1 high impedance after
precharge
tKHARPZ
—2
t
SYSCLK
3, 5,
6, 7
Notes:
1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge
of the input SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the
midpoint of the signal in question. All output timings assume a purely resistive 50-
load (see Figure 4). Input and
output timings are measured at the pin; time-of-flight delays must be added for trace lengths, vias, and connectors
in the system.
2. The symbology used for timing specifications herein follows the pattern of t(signal)(state)(reference)(state) for inputs and
t(reference)(state)(signal)(state) for outputs. For example, tIVKH symbolizes the time input signals (I) reach the valid state
(V) relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And tKHOV symbolizes the
time from SYSCLK(K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can be read
as the time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH) (note the position of
the reference and its state for inputs) and output hold time can be read as the time from the rising edge (KH) until
the output went invalid (OX).
3. tsysclk is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by the
period of SYSCLK to compute the actual time duration (in ns) of the parameter in question.
4. According to the bus protocol, TS is driven only by the currently active bus master. It is asserted low then
precharged high before returning to high impedance as shown in Figure 6. The nominal precharge width for TS is
0.5
× t
SYSCLK, that is, less than the minimum tSYSCLK period, to ensure that another master asserting TS on the
following clock will not contend with the precharge. Output valid and output hold timing is tested for the signal
asserted. Output valid time is tested for precharge. The high-impedance behavior is guaranteed by design.
5. Guaranteed by design and not tested.
6. According to the bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately
following AACK. Bus contention is not an issue because any master asserting ARTRY will be driving it low. Any
master asserting it low in the first clock following AACK will then go to high impedance for one clock before
precharging it high during the second cycle after the assertion of AACK. The nominal precharge width for ARTRY
is 1.0 tSYSCLK; that is, it should be high impedance as shown in Figure 6 before the first opportunity for another
master to assert ARTRY. Output valid and output hold timing is tested for the signal asserted. The high-impedance
behavior is guaranteed by design.
7. According to the MPX bus protocol, SHD0 and SHD1 can be driven by multiple bus masters beginning the cycle of
TS. Timing is the same as ARTRY, that is, the signal is high impedance for a fraction of a cycle, then negated for
up to an entire cycle (crossing a bus cycle boundary) before being three-stated again. The nominal precharge width
for SHD0 and SHD1 is 1.0 tSYSCLK. The edges of the precharge vary depending on the programmed ratio of
core-to-bus (PLL configurations).
8. BMODE[0:1] and BVSEL are mode select inputs and are sampled before and after HRESET negation. These
paramenters represent the input setup and hold times for each sample. These values are guaranteed by design
and not tested. These inputs must remain stable after the second sample. See Figure 5 for sample timing.
Table 9. Processor Bus AC Timing Specifications 1 (continued)
At recommended operating conditions. See Table 4.
Parameter
Symbol 2
All Speed Grades
Unit
Notes
Min
Max
Output
Z0 = 50
OVDD/2
RL = 50
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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