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| 型號： | MC7445ARX1000LG |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | RISC Microprocessor Hardware Specifications |
| 中文描述： | RISC微處理器硬件規(guī)格 |
| 文件頁數(shù)： | 31/64頁 |
| 文件大小： | 1127K |
| 代理商： | MC7445ARX1000LG |
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MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
Freescale Semiconductor
31
Electrical and Thermal Characteristics
Figure 13
provides the AC test load for TDO and the boundary-scan outputs of the MPC7455.
Figure 13. Alternate AC Test Load for the JTAG Interface
Figure 14
provides the JTAG clock input timing diagram.
Figure 14. JTAG Clock Input Timing Diagram
Figure 15
provides the TRST timing diagram.
Figure 15. TRST Timing Diagram
Valid times:
Boundary-scan data
TDO
t
JLDV
t
JLOV
4
4
20
25
ns
4
Output hold times:
Boundary-scan data
TDO
t
JLDX
t
JLOX
TBD
TBD
TBD
TBD
ns
4
TCK to output high impedance:
Boundary-scan data
TDO
t
JLDZ
t
JLOZ
3
3
19
9
ns
4, 5
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal
in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-
load
(see
Figure 13
). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
3. Non-JTAG signal input timing with respect to TCK.
4. Non-JTAG signal output timing with respect to TCK.
5. Guaranteed by design and characterization.
Table 14. JTAG AC Timing Specifications (Independent of SYSCLK)
1
(continued)
At recommended operating conditions. See
Table 4
.
Parameter
Symbol
Min
Max
Unit
Notes
Output
Z
0
= 50
OV
DD
/2
R
L
= 50
VM
VM
VM
VM = Midpoint Voltage (OV
DD
/2)
t
TCLK
t
JR
t
JF
t
JHJL
TCLK
TRST
t
TRST
VM = Midpoint Voltage (OV
DD
/2)
VM
VM
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