
Operation
MOTOROLA
Real-Time Clock
13-3
counter (9 bits) can count up to 512 days and is located in its own register (DAYR). The four counters can
be read at any time. The seconds, minutes, and hours data is maintained in 24-hour time format, which
increments to day counts.
Each of the four counters may be enabled to produce an interrupt on rollover. Upon reaching 59, the
seconds and minutes counters each produce an MIN or HR interrupt (when enabled) the next time they are
incremented. Both counters reset to 00 and increment the next counter. Likewise, the hours counter, after
reaching a count of 23, produces an interrupt (DAY) with the next increment from the minutes counter.
The counter resets to 00 and increments the day counter.
13.1.3 Alarm
The alarm is composed of four registers that mirror those found in the time-of-day counter. The seconds,
minutes, and hours counters are in the RTC alarm register (RTCALRM). The day alarm register
(DAYALRM) contains the 9-bit DAYSAL field.
An alarm is set by accessing the RTCALRM and DAYALRM register and loading the days, hours,
minutes, and seconds for the time that the alarm is to generate an interrupt. The alarm is enabled when the
ALM bit in the real-time interrupt enable register (RTCIENR) is set. When the time in the TOD counter
matches the time in the TOD alarm, the ALM bit in the real-time interrupt status register (RTCISR) is set.
If the alarm is not disabled, it will recur every 24 hours. If a single event alarm is desired, then the interrupt
service routine should change the values in the alarm registers or disable the ALM bit.
13.1.4 Watchdog Timer
The watchdog timer is an added check to ensure that a program is running and sequencing properly. When
application software is running, it is responsible for keeping the 2-second watchdog timer from timing out.
If the watchdog timer times out, it is an indication that the software is no longer being executed in the
intended sequence. At this time the watchdog timer generates either an interrupt or a reset signal to the
system.
Programming the watchdog timer (WATCHDOG) register determines if the 2-second rollover produces a
watchdog interrupt or a system reset. At reset, the watchdog timer is enabled and generates a system reset.
The watchdog timer is clocked by the 1 Hz clock from the prescaler and therefore has 1-second resolution.
It is recommended that the watchdog timer be periodically cleared by software once it is enabled.
Otherwise, either a software reset or watchdog interrupt will be generated when the timer reaches a binary
value of 10. The timer can be reset by writing any value into it.
13.1.5 Real-Time Interrupt Timer
There is a real-time interrupt available to the user. This interrupt will occur at one of eight different
selected rates. Applications for the real-time interrupt can include digitizer sampling, keyboard
debouncing, or communication polling.
Each of the eight real-time interrupts operates at a fixed frequency. The frequencies of the real-time
interrupts are shown in
Table 13-9, “Real-Time Interrupt Frequency Settings,” on page 14-215. Bits
RTE0–RTE7 in the RTC interrupt enable register (RTCIENR) enable each of the eight different predefined
rates. When the real-time interrupt occurs, it applies an interrupt which is configurable from level 1 to level
6 to the MC68SZ328 interrupt controller. The real-time clock (RTCEN bit in the RTCCTL) or the
watchdog timer (EN bit in the watchdog register) must be enabled for the real-time interrupt timer to
operate. If the RTC and watchdog timer are disabled, the real-time interrupt stops.