參數(shù)資料
型號(hào)： MC68SZ328
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： i.MX Integrated Portable System Processor
中文描述： i.MX處理器集成的便攜式系統(tǒng)
文件頁數(shù)： 86/96頁
文件大小： 1495K
代理商： MC68SZ328
MC9328MX1 Advance Information, Rev. 4
86
Freescale Semiconductor
Specifications
27b
STCK high to STXD low
9.12
18.24
8.0
16.0
ns
28
STCK high to STXD high impedance
18.47
28.5
16.2
25.0
ns
29
SRXD setup time before SRCK low
1.14
–
1.0
–
ns
30
SRXD hole time after SRCK low
0
–
0
–
ns
Synchronous Internal Clock Operation (Port C Primary Function)
2
31
SRXD setup before STCK falling
15.4
–
13.5
–
ns
32
SRXD hold after STCK falling
0
–
0
–
ns
Synchronous External Clock Operation (Port C Primary Function)
2
33
SRXD setup before STCK falling
1.14
–
1.0
–
ns
34
SRXD hold after STCK falling
0
–
0
–
ns
1.
All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a
non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync
STFS/SRFS shown in the tables and in the figures.
There are 2 sets of I/O signals for the SSI module. They are from Port C primary function (PC3 – PC8)
and Port B alternate function (PB14 – PB19). When SSI signals are configured as outputs, they can be
viewed both at Port C primary function and Port B alternate function. When SSI signals are configured as
input, the SSI module selects the input based on status of the FMCR register bits in the Clock controller
module (CRM). By default, the input are selected from Port C primary function.
bl = bit length; wl = word length.
2.
3.
Table 41. SSI 2 Timing Parameter Table
Ref
No.
Parameter
1.8V +/- 0.10V
3.0V +/- 0.30V
Unit
Minimum
Maximum
Minimum
Maximum
Internal Clock Operation
1
(Port B Alternate Function)
2
1
STCK/SRCK clock period
1
95
–
83.3
–
ns
2
STCK high to STFS (bl) high
3
1.7
4.8
1.5
4.2
ns
3
SRCK high to SRFS (bl) high
3
-0.1
1.0
-0.1
1.0
ns
4
STCK high to STFS (bl) low
3
3.08
5.24
2.7
4.6
ns
5
SRCK high to SRFS (bl) low
3
1.25
2.28
1.1
2.0
ns
Table 40. SSI 1 Timing Parameter Table (Continued)
Ref
No.
Parameter
1.8V +/- 0.10V
3.0V +/- 0.30V
Unit
Minimum
Maximum
Minimum
Maximum
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