參數(shù)資料
型號(hào): MC68SZ328
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: i.MX Integrated Portable System Processor
中文描述: i.MX處理器集成的便攜式系統(tǒng)
文件頁(yè)數(shù): 71/96頁(yè)
文件大?。?/td> 1495K
代理商: MC68SZ328
Specifications
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
71
Figure 54. SDIO ReadWait Timing Diagram
3.16 Memory Stick Host Controller
The Memory Stick protocol requires three interface signal line connections for data transfers: MS_BS, MS_SDIO,
and MS_SCLKO. Communication is always initiated by the MSHC and operates the bus in either four-state or
two-state access mode.
The MS_BS signal classifies data on the SDIO into one of four states (BS0, BS1, BS2, or BS3) according to its
attribute and transfer direction. BS0 is the INT transfer state, and during this state no packet transmissions occur.
During the BS1, BS2, and BS3 states, packet communications are executed. The BS1, BS2, and BS3 states are
regarded as one packet length and one communication transfer is always completed within one packet length (in
four-state access mode).
The Memory Stick usually operates in four state access mode and in BS1, BS2, and BS3 bus states. When an error
occurs during packet communication, the mode is shifted to two-state access mode, and the BS0 and BS1 bus states
are automatically repeated to avoid a bus collision on the SDIO.
DAT[1]
For 4-bit
DAT[2]
For 4-bit
CMD
******
PST
E Z Z
******
CMD52
Z
CRC
E Z Z
S
Block Data
L L L L L L L L L L L L L L L L L L L L L HZ S
E
S
Block Data
E
Block Data
Z Z L H
E
S
Block Data
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