參數(shù)資料
型號： MC68MH360VR25LR2
廠商： Freescale Semiconductor
文件頁數(shù)： 2/158頁
文件大小： 0K
描述： IC MPU QUICC 25MHZ 357-PBGA
標(biāo)準(zhǔn)包裝： 180
系列： M683xx
處理器類型： M683xx 32-位
速度： 25MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應(yīng)商設(shè)備封裝： 357-PBGA（25x25）
包裝： 帶卷 (TR)
QMC Supplement
ILLUSTRATIONS
Figure
Number
Title
Page
Number
5-7
MC68MH360 SCC1 Parameter RAM Usage ................................................................ 5-10
5-8
MC68MH360 SCC2 Parameter RAM Usage ................................................................ 5-11
5-9
MC68MH360 SCC3 Parameter RAM Usage ................................................................ 5-12
5-10
MC68MH360 SCC4 Parameter RAM Usage ................................................................ 5-13
5-11
MPC860MH Internal Memory ...................................................................................... 5-14
5-12
MPC860MH SCC1 Parameter RAM Usage.................................................................. 5-16
5-13
MPC860MH SCC2 Parameter RAM Usage.................................................................. 5-17
5-14
MPC860MH SCC3 Parameter RAM Usage.................................................................. 5-18
5-15
MPC860MH SCC4 Parameter RAM Usage.................................................................. 5-19
9-1
Two-Bit Subchannel Implementation without MSC Microcode ..................................... 9-2
9-2
Two-Bit Subchannel Implementation with MSC Microcode .......................................... 9-3
9-3
Time Slot Assignment Table Showing MSC Configuration ........................................... 9-4
9-4
Example for Eight 2-Bit Subchannels.............................................................................. 9-6
9-5
MPC860MH Internal Memory Map with MSC Microcode Enabled .............................. 9-7
A-1
Time Slot Assignment Table .......................................................................................... A-1
A-2
Time Slot Assignment Table for 64-Channel Common Rx and Tx Mapping................ A-2
A-3
CHAMR—Channel Mode Register (HDLC) ................................................................. A-3
A-4
Interrupt Table Entry and INTMSK (HDLC) ................................................................. A-3
A-5
TSTATE (HDLC) ........................................................................................................... A-3
A-6
RSTATE (HDLC)........................................................................................................... A-3
A-7
CHAMR—Channel Mode Register (Transparent Mode)............................................... A-4
A-8
INTMSK and Interrupt Table Entry (Transparent Mode) .............................................. A-4
A-9
TSTATE (Transparent Mode)......................................................................................... A-4
A-10
RSTATE (Transparent Mode) ........................................................................................ A-4
A-11
Command Register.......................................................................................................... A-4
A-12
SCC Event (SCCE) Register........................................................................................... A-5
A-13
SCCM Register ............................................................................................................... A-5
A-14
Receive Buffer Descriptor (RxBD) ................................................................................ A-5
A-15
Transmit Buffer Descriptor (TxBD) ............................................................................... A-5
C-1
IDL2 Bus Structure for a Connection to the QMC Bus...................................................C-2
C-2
IDL and SCP Connections between the QUICC32 and the S/T Interface.......................C-3
C-3
IDL and SCP Connections between the QUICC32 and the U Interface..........................C-4
C-4
FSC Generation from a 2.048-MHz Clock—Block Diagram .........................................C-6
C-5
FSC Generation from a 2.048-MHz Clock—Timing ......................................................C-6
C-6
Connection between Four S/T Interfaces and the QUICC32...........................................C-7
C-7
Timing Diagram for an Activation Initiated by the NT ...................................................C-9
C-8
Timing Diagram for an Activation Initiated by the TE .................................................C-10
C-9
Timing Diagram for a Deactivation (Always Initiated by the NT) ...............................C-11
C-10
Connection between Four U Interfaces and the QUICC32 ...........................................C-13
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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