參數(shù)資料
型號： MC68MH360CVR25L
廠商： Freescale Semiconductor
文件頁數(shù)： 43/158頁
文件大?。?/td> 0K
描述： IC MPU QUICC 25MHZ 357-PBGA
標(biāo)準(zhǔn)包裝： 44
系列： M683xx
處理器類型： M683xx 32-位
速度： 25MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應(yīng)商設(shè)備封裝： 357-PBGA（25x25）
包裝： 托盤
Appendix C. Connecting ISDN Multiple S/T or U Interfaces to QUICC32
Appendix C
Connecting ISDN Multiple
S/T or U Interfaces to QUICC32
C0
Using IDL or GCI protocols, the MC145574 (S/T interface) and the MC145572
(U interface) can be gluelessly interfaced to members of the MC68302 family for low-cost,
active-ISDN basic rate terminal applications.
For applications needing to support more than one basic rate interface (BRI), such as LAN/
WAN bridges, PBX, line cards or multiple-line terminal adaptors, a system solution using
multiple MC145574s or MC145572s can be built around a QUICC32 (MC68MH360).
The QUICC32 and the QMC (QUICC’s multichannel controller) protocol are useful for
such ISDN applications requiring several logical channels on one physical medium.
This appendix shows how multiple MC145574s or MC145572s can be connected to a
QUICC32, describing the level-1 connections and explaining the data ow through the
devices.
No software issues are addressed in this appendix.
C.1 The QMC Protocol
Based upon the IDL bus, the QMC protocol implemented on the QUICC32 generates a
TDM (time-division multiplexing) bus with programmable time slots for each ISDN
interface. With 32 time slots, each carrying 8 consecutive bits forming 64-Kbps channels,
a 2-Mbps TDM line (roughly equivalent to a CEPT/E1 link) can be created.
Time slot zero (TS0) is dedicated to the rst B1 channel, with TS1 assigned to the rst B2
channel and TS2 to the rst D channel. Even though only 2 bits are used for signaling, the
D channel has 8 bits reserved on the TDM link since the QMC microcode must process data
on 8-bit boundaries for correct delineation of channels. The unused 6 bits are masked in the
QMC time slot assignment table.
Since the TDM line allows a maximum of 32 channels, the above process of routing
channels to time slots (that is, the second B1 channel routed to TS3 and so on) can be
repeated for up to 10 BRIs.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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