AboutThis Book
About This Book
This document is a supplement to the MC68360 Quad Integrated Communications
Controller User’s Manual (MC68360UM/AD) and the MPC860 PowerQUICC User’s
Manual
(MPC860UM/AD).
It
replaces
the
MC68MH360
Reference
Manual
(MC68MH360RM/AD).
To locate any published errata or updates for this document, refer to the website at
http://www.mot.com/netcomm.
Audience
This manual is intended for system software and hardware developers. It is assumed that
the reader understands basic concepts of time-division-multiplexed processors and how the
MPC860 CPM operates.
Organization
Following is a summary and a brief description of the major sections of this manual:
Chapter 1, “Overview,” gives an introduction to the QMC (QUICC multichannel
controller) protocol including some example applications.
Chapter 2, “QMC Memory Organization,” describes the operation specic to the
QMC protocol.
Chapter 3, “QMC Commands,” discusses the transmit and receive commands.
Chapter 4, “QMC Exceptions,” describes QMC interrupt handling.
Chapter 5, “Buffer Descriptors,” describes the contents of the receive and transmit
buffer descriptors for the QMC protocol and discusses the placement of QMC and
non-QMC buffer descriptors in internal and external memory.
Chapter 6, “QMC Initialization,” discusses the essential steps to initialize QMC
after a hard reset.
Chapter 7, “Features Deleted in MC68MH360,” lists the features deleted from the
MH360.
Chapter 8, “Performance,” provides a performance table for common congurations
supported by the 860MH and/or MH360; covers general guidelines and examples
for determining the serial bit rate and CPM loading on a given system; and discusses
system bus utilization and arbitration.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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