Contents
iii
CONTENTS
Paragraph
Number
Title
Page
Number
Audience ................................................................................................................ xi
Organization........................................................................................................... xi
Additional Reading ............................................................................................... xii
Conventions .......................................................................................................... xii
Acronyms and Abbreviations .............................................................................. xiii
Chapter 1
Overview
1.1
The QMC (QUICC Multichannel Controller) ..................................................... 1-1
1.2
Introduction.......................................................................................................... 1-1
1.3
QMC Features...................................................................................................... 1-3
1.4
The Time Slot Assigner and the QMC ................................................................ 1-4
1.5
The Serial Interface (SI)....................................................................................... 1-4
1.5.1
Synchronization ............................................................................................... 1-5
1.5.2
Loopback Mode ............................................................................................... 1-5
1.5.3
Echo Mode ....................................................................................................... 1-5
1.5.4
Inverted Signals ............................................................................................... 1-5
1.6
QMC Serial Routing and Example Applications................................................. 1-6
1.7
SCC Changes on the Fly .................................................................................... 1-10
1.8
SI RAM Errors................................................................................................... 1-10
1.9
E1/T1 Frame Description................................................................................... 1-11
Chapter 2
QMC Memory Organization
2.1
QMC Memory Structure ...................................................................................... 2-2
2.1.1
Dual-Ported RAM Base ................................................................................... 2-3
2.1.2
SCC Base and Global Multichannel Parameters ............................................. 2-3
2.1.3
TSATRx/TSATTx Pointers and Time Slot Assignment Table ....................... 2-3
2.1.4
TSATRx/TSATTx Channel Pointers............................................................... 2-4
2.1.5
Logical Channel TBASE and RBASE............................................................. 2-4
2.1.6
MCBASE ......................................................................................................... 2-4
2.1.7
Buffer Descriptor Table ................................................................................... 2-4
2.1.8
Data Buffer Pointer .......................................................................................... 2-5
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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