
Technical Data
MC68HC705C8A 
—
 Rev. 3
62
Resets
MOTOROLA
Resets
5.3.1  Power-On Reset (POR) 
A positive transition on the V
DD
pin generates a power-on reset (POR). 
The POR is strictly for the power-up condition and cannot be used to 
detect drops in power supply voltage.
A 4064 t
CYC
(internal clock cycle) delay after the oscillator becomes 
active allows the clock generator to stabilize. If the RESET pin is at 
logic 0 at the end of 4064 t
CYC
, the MCU remains in the reset condition 
until the signal on the RESET pin goes to logic 1. 
5.3.2  External Reset
The minimum time required for the MCU to recognize a reset is 1 1/2 
t
CYC
.
However, to guarantee that the MCU recognizes an external reset 
as an external reset and not as a COP or clock monitor reset, the RESET 
pin must be low for eight t
CYC
. After six t
CYC
, the input on the RESET pin 
is sampled. If the pin is still low, an external reset has occurred. If the 
input is high, then the MCU assumes that the reset was initiated 
internally by either the COP watchdog timer or by the clock monitor. This 
method of differentiating between external and internal reset conditions 
assumes that the RESET pin will rise to a logic 1 less than two t
CYC
 after 
its release and that an externally generated reset should stay active for 
at least eight t
CYC
. 
5.3.3  Programmable and Non-Programmable COP Watchdog Resets 
A timeout of a COP watchdog generates a COP reset. A COP watchdog, 
once enabled, is part of a software error detection system and must be 
cleared periodically to start a new timeout period. 
The MC68HC705C8A has two different COP watchdogs for compatibility 
with devices such as the MC68HC705C8 and the MC68HC05C4A:
1.
Programmable COP watchdog reset
2.
Non-programmable COP watchdog
One COP has four programmable timeout periods and the other has a 
fixed non-programmable timeout period.