
Technical Data
MC68HC705C8A 
—
 Rev. 3
144
Serial Peripheral Interface (SPI)
MOTOROLA
Serial Peripheral Interface (SPI)
11.4.2  Pin Functions in Slave Mode
Clearing the MSTR bit in the SPCR configures the SPI for operation in 
slave mode. The slave-mode functions of the SPI pins are:
PD4/SCK (serial clock) 
—
 In slave mode, the PD4/SCK pin is the 
input for the synchronizing clock signal from the master SPI. 
PD3/MOSI (master output, slave input) 
—
 In slave mode, the 
PD3/MOSI pin is the serial input.
PD2/MISO (master input, slave output) 
—
 In slave mode, the 
PD2/MISO pin is the serial output.
PD5/SS (slave select) 
—
 In slave mode, the PD5/SS pin enables 
the SPI for data and serial clock reception from a master SPI.
When CPHA = 0, the shift clock is the OR of SS with SCK. In this clock 
phase mode, SS must go high between successive characters in an SPI 
message. When CPHA = 1, SS may be left low for several SPI 
characters. In cases with only one SPI slave MCU, the slave MCU SS 
line can be tied to V
SS
 as long as CPHA = 1 clock modes are used. 
The WCOL flag bit can be improperly set when attempting the first 
transmission after a reset if these conditions are present: MSTR = 0, 
CPOL = 0, CPHA = 1, SS pin = 0, and SCK pin = 1. The reset states of 
the CPOL and CPHA bits are 0 and 1, respectively. Under normal 
operating conditions (CPOL = 0, CPHA = 1), the SCK input will be low.
The incorrect setting of the WCOL bit can be prevented in two ways:
1.
Send a dummy transmission after reset, clear the WCOL flag, and 
then proceed with the real transmission.
2.
Use the MSTR bit in the SPCR (SPI control register). This is 
accomplished by setting the MSTR bit at the same time the CPOL 
and CPHA bits are programmed to the desired logic levels. Then, 
the data register can be written to if desired. After this, the MSTR 
bit should be set to a logic 0, the SPE (SPI enable bit) should be 
set to a logic 1, and the CPOL, CPHA, SPR1, and SPR0 bits set 
to the desired logic levels. If this procedure is followed after a reset 
and before the first access to the SPDR, the WCOL flag will not be 
set.