- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67966 > MC68HSC05C9AFN (MOTOROLA INC) 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PQCC44 PDF資料下載
參數(shù)資料
| 型號： | MC68HSC05C9AFN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 100/162頁 |
| 文件大?。?/td> | 1093K |
| 代理商： | MC68HSC05C9AFN |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁當前第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁
N
O
N-D
I
SC
L
O
SU
R
E
AG
R
EEMENT
R
E
Q
U
IR
ED
Interrupts
Advance Information
MC68HC05C9A — Rev. 5.0
42
Interrupts
MOTOROLA
Unlike RESET, hardware interrupts do not cause the current instruction
execution to be halted, but are considered pending until the current
instruction is complete.
NOTE:
The current instruction is the one already fetched and being operated on.
When the current instruction is complete, the processor checks all
pending hardware interrupts. If interrupts are not masked (CCR I bit
clear) and if the corresponding interrupt enable bit is set, the processor
proceeds with interrupt processing; otherwise, the next instruction is
fetched and executed.
If an external interrupt and a timer, SCI, or SPI interrupt are pending at
the end of an instruction execution, the external interrupt is serviced first.
The SWI is executed the same as any other instruction, regardless of the
I-bit state.
Table 4-1 shows the relative priority of all the possible interrupt sources.
Figure 4-1 shows the interrupt processing flow.
4.3 Non-Maskable Software Interrupt (SWI)
The SWI is an executable instruction and a non-maskable interrupt. It is
executed regardless of the state of the I bit in the CCR. If the I bit is 0
(interrupts enabled), SWI executes after interrupts which were pending
when the SWI was fetched, but before interrupts generated after the SWI
was fetched. The interrupt service routine address is specified by the
contents of memory locations $3FFC and $3FFD.
4.4 External Interrupt (IRQ or Port B)
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts
(internal and external) are disabled. Clearing the I bit enables interrupts.
The interrupt request is latched immediately following the falling edge of
IRQ. It is then synchronized internally and serviced as specified by the
contents of $3FFA and $3FFB.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HC05E0 | 8-BIT, 4 MHz, MICROCONTROLLER, PQCC68 |
| MC68HC05F2FB | 8-BIT, MROM, MICROCONTROLLER, PQFP44 |
| MC68HC05F2B | 8-BIT, MROM, MICROCONTROLLER, PDIP42 |
| MC68HC705F6FU | 8-BIT, OTPROM, MICROCONTROLLER, PQFP64 |
| MC68HC05F6B | 8-BIT, MROM, MICROCONTROLLER, PDIP42 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HSC705C8ACFB | 制造商:Rochester Electronics LLC 功能描述:8 BIT MCU, 304 BYTES RAM - Bulk |
| MC68HSC705C8ACP | 制造商:Rochester Electronics LLC 功能描述: 制造商:Freescale Semiconductor 功能描述: |
| MC68HSC705C8ACS | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC68HSC705J1ACDW | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC68HSC705J1ACP | 制造商:Rochester Electronics LLC 功能描述:8 BIT MCU, 64 BYTES RAM - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。