參數(shù)資料
型號： MC68HSC05C9ACP
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁數(shù)： 60/162頁
文件大?。?/td> 1093K
代理商： MC68HSC05C9ACP
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MC68HSC05C9A
Advance Information
MC68HC05C9A — Rev. 5.0
152
MC68HSC05C9A
MOTOROLA
B.5.3 4.5–5.5-Volt High-Speed Control Timing
Num
Characteristic(1)
Symbol
Min
Max
Unit
Operating frequency
Master
Slave
fOP(M)
fOP(S)
dc
0.5
4.1
fOP
MHz
1
Cycle time
Master
Slave
tcyc(M)
tcyc(S)
2.0
244
—
tcyc
ns
2
Enable lead time
Master
Slave
tLead(M)
tLead(S)
Note(2)
122
—
ns
3
Enable lag time
Master
Slave
tLag(M)
tLag(S)
Note(2)
366
—
ns
4
Clock (SCK) high time
Master
Slave
tW(SCKH)M
tW(SCKH)S
166
93
—
ns
5
Clock (SCK) low time
Master
Slave
tW(SCKL)M
tW(SCKL)S
166
93
—
ns
6
Data setup time (inputs)
Master
Slave
tSU(M)
tSU(S)
49
—
ns
7
Data hold time (inputs)
Master
Slave
tH(M)
tH(S)
49
—
ns
8
Slave access time (time to data active from
high-impedance state)
tA
061
ns
9
Slave disable time (hold time to high-impedance state)
tDIS
—
122
ns
10
Data valid
Master (before capture edge)
Slave (after enable edge)(3)
tV(M)
tV(S)
0.25
—
122
tcyc(M)
ns
11
Data hold time (outputs)
Master (after capture edge)
Slave (after enable edge)
tHO(M)
tHO(S)
0.25
0
—
tcyc(M)
ns
12
Rise time (20% VDD to 70% VDD, CL = 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
tRM
tRS
—
50
1.0
ns
s
13
Fall time (70% VDD to 20% VDD, CL = 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
tFM
tFS
—
50
1.0
ns
s
1. VDD = 4.5–5.5 Vdc
2. Signal production depends on software.
3. Assumes 200 pF load on all SPI pins
相關(guān)PDF資料
PDF描述
MC68HC05C9AMP 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40
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