參數(shù)資料
型號: MC68HRC705JP7CP
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP28
封裝: PLASTIC, DIP-28
文件頁數(shù): 136/164頁
文件大小: 1165K
代理商: MC68HRC705JP7CP
Analog Multiplex Register
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
73
8.2 Analog Multiplex Register
The analog multiplex register (AMUX) controls the general interconnection and operation. The control bits
in the AMUX are shown in Figure 8-2.
HOLD, DHOLD
These read/write bits control the source connection to the negative input of voltage comparator 2
shown in Figure 8-3. This allows the voltage on the internal temperature sensing diode, the channel
selection bus, or the divide-by-two channel selection bus to charge the internal sample capacitor and
to also be presented to comparator 2. The decoding of these sources is given in Table 8-1.
During the hold case when both the HOLD and DHOLD bits are clear, the VOFF bit in the analog status
register (ASR) can offset the VSS reference on the sample capacitor by approximately 100 mV. This
offset source is bypassed whenever the sample capacitor is being charged with either the HOLD or
DHOLD bit set. The VOFF bit must be enabled by the OPT bit in the COPR at location $1FF0.
Figure 8-3. Comparator 2 Input Circuit
Address:
$0003
Bit 7
654321
Bit 0
Read:
HOLD
DHOLD
INV
VREF
MUX4
MUX3
MUX2
MUX1
Write:
Reset:
10000000
Figure 8-2. Analog Multiplex Register (AMUX)
+
COMP2
SAMPLE
HOLD
DHOLD
CAP
TEMPERATURE
DIODE
INTERNAL
VOFF
VSS
OFFSET
+
OPT (MOR)
CHANNEL
PB0
SELECTION
BUS
VDD
80 k
80 k
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