參數(shù)資料
型號： MC68HRC705JP7CP
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP28
封裝： PLASTIC, DIP-28
文件頁數(shù)： 125/164頁
文件大?。?/td> 1165K
代理商： MC68HRC705JP7CP
Port B
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
63
7.3.7 PB5/SDO Logic
The PB5/SDO pin can be used as a simple I/O port pin or be controlled by the SIOP serial interface as
shown in Figure 7-10. The operations of the PB5 pin are summarized in Table 7-3.
When using the PB5/SDO pin, these interactions must be noted:
1.
If the SIOP function is required, then the SPE bit in the SCR must be set. This causes the PB5/SDO
pin buffer to be enabled and to be driven by the serial data output (SDO) from the SIOP. The
pulldown device will be disabled in this case.
2.
If the SIOP function is in control of the PB5/SDO pin, the DDRB5 and PB5 data register bits are
still accessible to the CPU and can be altered or read without affecting the SIOP functionality.
However, if the DDRB5 bit is cleared, reading the PB5 data register will return the current state of
the PB5/SDO pin.
Figure 7-10. PB5/SDO Pin I/O Circuit
3.
If the SIOP function is terminated by clearing the SPE bit in the SCR, then the last conditions stored
in the DDRB5, PDIB5, and PB5 register bits will then control the PB5/SDO pin.
4.
If the PB5/SDO pin is to be a digital input, then both the SPE bit in the SCR and the DDRB5 bit
must be cleared. Depending on the external application, the pulldown device may also be disabled
by setting the PDIB5 pulldown inhibit bit.
5.
If the PB5/SDO pin is to be a digital output, then the SPE bit in the SCR must be cleared and the
PDIB5 bit must be set. The pulldown device will be disabled in this case.
DATA DIRECTION
REGISTER B
BIT DDRB5
PORT B DATA
REGISTER
BIT PB5
PULLDOWN
REGISTER B
BIT PDIB5
R
PB5
READ $0005
WRITE $0001
READ $0001
WRITE $0011
PULLDOWN
DEVICE
RESET
INTE
RNAL
D
AT
A
B
U
S
WRITE $0005
SDO
SERIAL ENABLE (SPE)
SERIAL DATA OUT (SDO)
VDD
SWPDI
MASK OPTION REG. ($1FF1)
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