參數(shù)資料
型號(hào): MC68HCL05P1ADWR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: SOIC-28
文件頁數(shù): 93/124頁
文件大?。?/td> 623K
代理商: MC68HCL05P1ADWR2
NON-DISCLOSURE
AGREEMENT
REQUIRED
16-Bit Timer
General Release Specification
MC68HC05P1A Rev. 3.0
70
16-Bit Timer
MOTOROLA
Figure 8-7. Output Compare Software Initialization Example
Figure 8-8. State Timing Diagram for Output Compare
9B
.
B6
BE
B7
B6
BF
.
9A
.
XX
16
13
17
.
SEI
.
LDA
LDX
STA
LDA
STX
.
CLI
.
DATAH
DATAL
OCRH
TSR
OCRL
.
BLOCK INTERRUPTS
.
HI BYTE FOR COMPARE
LO BYTE FOR COMPARE
INHIBIT OUTPUT COMPARE
ARM OCF BIT TO CLEAR
READY FOR NEXT COM-
PARE
.
NOTES:
1.
The CPU write to the compare register may take place at any time, but a compare only occurs at timer state T01. Thus, up
to a four cycle difference may exist between the write to the compare register and the actual compare.
2.
Internal compare takes place during timer state T01.
3.
The output compare ag bit (OCF) is set at timer state T11 which follows the comparison match ($FFED in this example).
OUTPUT
COMPARE FLAG
AND OUTPUT PIN
16-BIT FREE-
RUNNING
COUNTER
COMPARE
REGISTER
COMPARE
REGISTER
LATCH
PH2
CLOCK
$FFEB
$FFEC
$FFED
$FFEE
$FFEF
CPU WRITES $FFED
$FFED
(NOTE 1)
(NOTE 2)
(NOTE 3)
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