參數(shù)資料
型號: MC68HCL05P1ADWR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: SOIC-28
文件頁數(shù): 54/124頁
文件大小: 623K
代理商: MC68HCL05P1ADWR2
CPU Core
CPU Registers
MC68HC05P1A Rev. 3.0
General Release Specification
MOTOROLA
CPU Core
35
NON-DISCLOSURE
AGREEMENT
REQUIRED
I — Interrupt
When this bit is set, the timer and external interrupt are masked
(disabled). If an interrupt occurs while this bit is set, the interrupt is
latched and processed as soon as the I bit is cleared.
N — Negative
When set, this bit indicates that the result of the last arithmetic, logical,
or data manipulation was negative.
Z — Zero
When set, this bit indicates that the result of the last arithmetic, logical,
or data manipulation was zero.
C — Carry/Borrow
When set, this bit indicates that a carry or borrow out of the arithmetic
logical unit (ALU) occurred during the last arithmetic operation. This
bit is also affected during bit test and branch instructions and during
shifts and rotates.
相關(guān)PDF資料
PDF描述
MC68HC05P1P 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28
MC68HC05P3CDW 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
MC68HC05P3P 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28
MC68HC05P3CP 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28
MC68HC05P3DW 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
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