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參數(shù)資料
| 型號(hào)： | MC68HC805K3DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, EEPROM, 2 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁(yè)數(shù)： | 37/119頁(yè) |
| 文件大?。?/td> | 496K |
| 代理商： | MC68HC805K3DW |
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General Release Specication
Functional Pin Description
MC68HC805K3 — Rev. 1.0
24
General Description
MOTOROLA
1.7.3 Reset (RESET)
This pin can be used as an input to reset the MCU to a known startup
state by pulling the pin to the low state. The RESET pin contains a
steering diode to discharge any voltage on the pin to VDD when the
power is removed. The RESET pin contains an internal pullup resistor to
VDD of approximately 100 k to allow the RESET pin to be left
unconnected for low-power applications. The RESET pin contains an
internal Schmitt trigger to improve its noise immunity as an input.
The RESET pin has an internal pulldown device that pulls the RESET
pin low when there is an internal COP watchdog or an illegal address
reset. Refer to Section 5. Resets.
1.7.4 Maskable Interrupt Request (IRQ)
The IRQ input pin drives the asynchronous IRQ interrupt function of the
CPU. The IRQ interrupt function has a mask option register bit to select
either negative edge-sensitive triggering or both negative edge-sensitive
and low level-sensitive triggering. If the option is selected to include
level-sensitive triggering, the IRQ pin requires an external resistor to
V
DD if “wired-OR” operation is desired. If the IRQ pin is not used, it must
be tied to the VDD supply.
NOTE:
Each of the PA0 through PA3 I/O pins can be connected through an OR
gate to the IRQ interrupt function by a common mask option. This
capability allows keyboard scan applications where the transitions or
levels on the I/O pins behave the same as the IRQ pin, except that the
logic level is inverted. The edge or level sensitivity selected by the mask
option register bit for the IRQ pin also applies to the I/O pins ORed to
create an IRQ signal.
The IRQ pin contains an internal Schmitt trigger to improve noise
immunity. For more details, see Section 4. Interrupts.
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