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| 型號(hào)： | MC68HC705V8B |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | SDIP-56 |
| 文件頁(yè)數(shù)： | 50/172頁(yè) |
| 文件大?。?/td> | 890K |
| 代理商： | MC68HC705V8B |
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MOTOROLA
SECTION 15: MESSAGE DATA LINK CONTROLLER
Page 132
MC68HC705V8 Specification Rev. 2.1
impedance construction, with regard to high frequencies, and placed as close as is
physically possible to the supply pins of the MDLC. See Motorola application note
Designing for EMC with HCMOS Microcontrollers (AN1050) for more help on this matter.
15.7
MDLC APPLICATION NOTES
15.7.1
INITIALIZATION
The MCU will first write to the MDLC Control Register (MCR). This byte should configure
the rate select bits to configure the MUX Interface clock to its nominal value, and set the
Interrupt Enable bit if desired.
15.7.2
TRANSMITTING A MESSAGE
The MDLC is ready for loading of a new message for transmission when the TXMS bit in
the MDLC Status Register (MSR) is set to a 1, or had been set but was cleared by a
subsequent access of the MDLC Transmit Control Register (MTCR). The MCU will first load
bytes for transmission into the Tx Buffer. Once the data bytes have been loaded, the MCU
will then write the transmit count to the MTCR register. This will command the MDLC to
begin transmission on the J1850 bus at the next idle bus period. The MDLC will
automatically calculate and append a CRC to the last byte of the transmitted message.
If the IE bit was set in the MCR register an interrupt request will be generated for the receipt
of this message from the J1850 bus. The MCU should clear the interrupt by an access (read
or write) to the MTCR register. The TXMS and RXMS bits in the MSR register will be set
by the MDLC upon reception of this message. The TXMS bit is cleared by any access (read
or write) of the MTCR register. The RXMS bit is cleared by any access (read or write) of the
MDLC Receive Status Register (MRSR). The MDLC is now available to transmit another
message.
A transmitting node should verify the correct transmission of its message by waiting for the
Transmit Message Successful (TXMS) bit to be set in the MSR register. The only way to
check for incorrect transmission of a message is for the MCU to provide a time-out if the
TXMS bit is not set in a certain length of time. This is the only way to detect the
unsuccessful transmission of a message, because any received message with errors is
neither stored nor indicated as received in error by the MDLC.
15.7.3
RECEIVING A MESSAGE
When a complete message is received by the MDLC error-free from the SAE J1850 bus,
the RXMS bit in the MSR will be set. In addition, if the IE bit in the MCR is set, a CPU
interrupt request will be generated. The RXMS bit and the CPU interrupt are cleared by an
access (read or write) of the MRSR register, unless a second message has also been
received from the SAE J1850 bus and is waiting to be retrieved.
The MCU may extract received message bytes from the MDLC by reading successive Rx
Buffer locations beginning at the lowest address location of the Rx Buffer. The received
message bytes can be accessed any number of times, in any order, by the CPU. The CPU
can determine the number of bytes to read by the Receive Count indicated in the MRSR
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