
MOTOROLA
Page x
MC68HC705V8 Specification Rev. 2.1
Figure 8-1:
Stop Recovery Timing Diagram .......................................................... 64
Figure 8-2:
STOP/WAIT Flowcharts ...................................................................... 65
Figure 9-1:
Port A and Port C I/O Circuitry ............................................................ 67
Figure 9-2:
Port B I/O Circuitry .............................................................................. 69
Figure 9-3:
Port D and Port E Circuitry .................................................................. 70
Figure 10-1:
A/D Status and Control Register ......................................................... 72
Figure 10-2:
A/D Data Register ............................................................................... 73
Figure 11-1:
16-Bit Timer Block Diagram ................................................................ 75
Figure 11-2:
TCAP Timing ....................................................................................... 77
Figure 11-3:
Timer Control Register - $12 ............................................................... 78
Figure 11-4:
Timer Status Register - $13 ................................................................ 79
Figure 12-1:
Core Timer Block Diagram .................................................................. 81
Figure 12-2:
Core Timer Control and Status Register ............................................. 82
Figure 12-3:
Timer Counter Register ....................................................................... 84
Figure 13-1:
PWM Block Diagram ........................................................................... 85
Figure 13-2:
PWM Waveform Examples (POL = 1)................................................. 86
Figure 13-3:
PWM Waveform Examples (POL = 0)................................................. 86
Figure 13-4:
PWM Write Sequences ....................................................................... 87
Figure 13-5:
PWM Control Register ........................................................................ 87
Figure 13-6:
PWM Data Register ............................................................................ 88
Figure 14-1:
Data Clock Timing Diagram ................................................................ 90
Figure 14-2:
Serial Peripheral Interface Block Diagram .......................................... 92
Figure 14-3:
Serial Peripheral Interface Master-Slave Interconnection ................... 93
Figure 14-4:
SPI Control Register (SPCR) .............................................................. 93
Figure 14-5:
Serial Peripheral Rate Selection ......................................................... 94
Figure 14-6:
SPI Status Register (SPSR)................................................................ 94
Figure 15-1:
MDLC Operating Modes State Diagram ............................................. 99
Figure 15-2:
MDLC User Registers ....................................................................... 101
Figure 15-3:
MDLC Control Register (MCR) ......................................................... 102
Figure 15-4:
MDLC Status Register (MSR) ........................................................... 105
Figure 15-5:
MDLC Tx Control Register (MTCR) .................................................. 106
Figure 15-6:
MDLC Rx Status Register (MRSR) ................................................... 107
Figure 15-7:
MDLC Rx/Tx Buffers Outline ............................................................. 110
Figure 15-8:
MDLC Protocol Handler Outline ........................................................ 113
Figure 15-9:
MDLC Rx Digital Filter Block Diagram .............................................. 118
Figure 15-10:
J1850 Bus Message Format (VPW).................................................. 119
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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