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參數(shù)資料
| 型號(hào)： | MC68HC705V8B |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | SDIP-56 |
| 文件頁(yè)數(shù)： | 126/172頁(yè) |
| 文件大小： | 890K |
| 代理商： | MC68HC705V8B |
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MOTOROLA
SECTION 6: RESETS
Page 46
MC68HC705V8 Specification Rev. 2.1
The RESET pin can also act as an open drain output. It will be pulled to a low state by an
internal pulldown that is activated by any reset source. This RESET pulldown device will
only be asserted for 3-4 cycles of the internal clock, PH2 (PH2 period = E clock period) or
as long as an internal reset source is asserted. When the external RESET pin is asserted,
the pulldown device will be turned on for only the 3-4 internal clock cycles.
6.2
INTERNAL RESETS
The five internally generated resets are the initial power-on reset function, the COP
Watchdog Timer reset, the illegal address detector, the low-voltage reset, and the disabled
STOP instruction. Termination of the external RESET input or the internal COP Watchdog
Timer are the only reset sources that can alter the operating mode of the MCU. The other
internal resets will not have any effect on the mode of operation when their reset state ends.
All internal resets will also assert (pull to logic zero) the external RESET pin for the duration
of the reset or 3-4 internal clock cycles, whichever is longer.
6.2.1
POWER-ON RESET (POR)
The internal POR is generated on power-up to allow the clock oscillator to stabilize. The
POR is strictly for power turn-on conditions and is not able to detect a drop in the power
supply voltage (brown-out). There is an oscillator stabilization delay of 4064 internal
processor bus clock cycles (PH2) after the oscillator becomes active.
The POR will generate the RST signal which will reset the CPU. If any other reset function
is active at the end of this 4064 cycle delay, the RST signal will remain in the reset condition
until the other reset condition(s) end.
POR will activate the RESET pin pulldown device connected to the pin. VDD must drop
below VPOR in order for the internal POR circuit to detect the next rise of VDD.
6.2.2
OPERATION IN STOP AND WAIT
If enabled, the LVR supply voltage sense option is active during STOP and WAIT. Any reset
source can bring the MCU out of STOP or WAIT modes.
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Freescale Semiconductor, Inc.
For More Information On This Product,
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