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參數(shù)資料
| 型號： | MC68HC705V8 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁數(shù)： | 8/28頁 |
| 文件大?。?/td> | 220K |
| 代理商： | MC68HC705V8 |
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MOTOROLA
8
AN1224/D
interrupts of the CPU, and to control how the MDLC module will operate when the WAIT instruction has
been executed by the CPU. The MCR also contains the transmit abort (TXAB) control bit, which enables
the user to abort a transmission which is in progress, allowing a different message, possibly one of higher
priority, to then be transmitted. The MDLC Transmit Control Register (MTCR) is used to indicate to the
MDLC module that a new message is in the transmit buffer awaiting transmission, and how many bytes are
to be transmitted.
The MDLC Status Register (MSR) contains two status bits, one which indicates when a message has been
transmitted successfully onto the multiplex bus, and another to indicate that a new message has been
received from the multiplex bus. If MDLC interrupts of the CPU have been enabled, whenever either of
these two bits is set an interrupt of the CPU will occur. When a received message is made available to the
CPU, the MDLC Receive Status Register (MRSR) contains the number of bytes in the received message.
Transmit Message Buffer Operation
The MDLC contains a single buffer for storing messages for transmission onto the multiplex bus, located in
the MC68HC705V8 I/O registers memory map at locations $20-$2A. This transmit (Tx) buffer is an 11-byte
buffer into which the CPU loads all necessary header and data bytes to be transmitted onto the multiplex
bus. This allows the MDLC to transmit the maximum frame length allowed by J1850 (11 bytes + CRC byte).
The CRC byte is automatically calculated and appended onto the frame by the MDLC following
transmission of the last data byte.
The Tx buffer can only hold one complete message at a time. Once a complete message has been loaded
into the Tx buffer, the CPU then writes the number of bytes to be transmitted into the MTCR. Once this is
done, the user should never attempt to write further data to the Tx buffer until the message has been
successfully transmitted, or discarded. If the transmission attempt has been successful, the TXMS bit in
the MSR will be set, and an interrupt of the CPU will occur, if interrupts are enabled. If the CPU wishes to
transmit a new message before the current one has been transmitted, it can empty the Tx buffer by setting
the transmit abort (TXAB) bit in the MCR. This will clear the Tx buffer, aborting any transmission in
progress. Once the TXAB bit has been reset, indicating that the transmit abort process is complete, the
CPU can then begin loading new message bytes into the Tx buffer.
If an error is detected during a transmission onto the multiplex bus, the MDLC will immediately halt
transmission. No attempt will be made to retransmit the message, and the Tx buffer will be cleared and
again made available to the CPU. No indication will be given to the CPU that the transmission was
unsuccessful. Any time a loss of arbitration is detected during a transmission, the MDLC will also
immediately halt transmission. However, once an idle bus condition is detected, the MDLC will attempt to
retransmit the message onto the multiplex bus.
Receive Message Buffers Operation
The MDLC contains two buffers for storing messages received from the multiplex bus. Each buffer can hold
up to 11 bytes, allowing the MDLC to also receive the maximum frame length allowed by J1850 (11 bytes +
CRC byte). The receive buffers are both located at memory locations $34–$3E. These receive (Rx) buffers
can each store a complete, maximum-length J1850 message (without the CRC). The MDLC will only place
a message which has been received from the multiplex bus error-free into an Rx buffer. Any message in
which an error is detected will be discarded, and the CPU will not be notified. Once the MDLC has placed
a complete message in an Rx buffer, it makes this Rx buffer available to the CPU while denying the CPU
access to the other Rx buffer until the next message has been received. Since only one of these Rx buffers
can be accessed by the CPU at a time, to the user there appears to be only a single Rx buffer. This "ping-
pong" action allows the MDLC to store a message being received from the multiplex bus in one Rx buffer
while the user is retrieving a previously received message from the other Rx buffer.
When a message is received by the MDLC and placed into an Rx buffer, the user is notified via the RXMS
bit in the MSR register, and an interrupt of the CPU is generated, if MDLC interrupts are enabled. Any
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