參數(shù)資料
型號: MC68HC705V8
廠商: Motorola, Inc.
英文描述: 8-Bit Microcontroller Units (MCU).(8位微控制器)
中文描述: 8位微控制器單元(MCU)。(8位微控制器)
文件頁數(shù): 14/28頁
文件大?。?/td> 220K
代理商: MC68HC705V8
MOTOROLA
14
AN1224/D
Figure 6. Real Time Interrupt Service Routine
Receiving
When the MDLC has received an error-free message from the multiplex bus, the MDLC interrupt service
routine performs the necessary message filtering and data retrieval. If the received message passes the
message filtering criteria, the message data bytes are stored in MCR RAM. If the received message does
not meet the message filtering criteria, the message is discarded.
As soon as a received message is stored in one of the MDLC's two Rx buffers, a received message
(RXMS) interrupt of the CPU is generated. The interrupt service routine first tests bit 2 of the first byte of
the message. The first byte of the message is the Priority/Type byte in the 3-byte consolidated header
format defined in SAE J1850. Bit 2 is the Type bit, which is used to indicate whether the message is
functionally addressed or physically addressed. If this bit is set, indicating that the message is a physically
addressed message, the second byte of the message, the target address byte, is compared to the node
address. If the target address of the message matches the physical address of the node, the message
data bytes are retrieved and stored in MCU RAM beginning at location "nbuff", and the third byte of the
message, the physical address of the message originator, is stored in MCU RAM location "nsource". If the
target address of the received message does not match the physical address of the node, a write to the
MRSR is performed, clearing the RXMS interrupt and releasing the Rx buffer back to the MDLC, effectively
discarding the message.
RTI INTERRUPT
OCCURS
IS VALUE IN
RAM LOCATION
"rticnt" =7
NO
YES
IS TXAB BIT IN
MCR CLEAR
YES
NO
RETURN FROM
INTERRUPT
WRITE "1" TO RTFC BIT
IN CTCSR TO CLEAR RTI
INTERRUPT FLAG
INCREMENT RAM
LOCATION "rticnt"
SET TXAB BIT IN MCR
TO ABORT MDLC
TRANSMISSION
CLEAR RTIE BIT IN
CTCSR, DISABLING
REAL TIME INTERRUPT
CLEAR RAM
LOCATION "rticnt"
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