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參數(shù)資料
| 型號： | MC68HC705V8 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁數(shù)： | 12/28頁 |
| 文件大?。?/td> | 220K |
| 代理商： | MC68HC705V8 |
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MOTOROLA
12
AN1224/D
Transmitting
To transmit a message onto the multiplex bus using the MDLC, the CPU simply stores the message bytes
and message byte count into the correct MCU RAM locations and then calls the TRANSMIT subroutine.
The software handles moving the data from MCU RAM storage into the MDLC Tx buffer, initiating the
message transmission, and determining when the message has been transmitted successfully.
When the application has data to be transmitted onto the multiplex bus, the user stores the message bytes,
including the header bytes, into MCU RAM, beginning at location "txbuf". The total number of bytes in the
message to be transmitted is then loaded into the RAM location "txcount". The user then calls the
subroutine TRANSMIT. This subroutine will transfer the new message bytes to the MDLC module for
transmission onto the multiplex bus, and then load the number of bytes to be transmitted into the MTCR,
initiating the message transmission.
Figure 5 Example Transmit Sequence
illustrates the sequence used
by this example software to transmit a message onto the multiplex bus.
Once the message transmission has been initiated, the TRANSMIT subroutine will then enable the real
time interrupt (RTI) function of the Core Timer. The RTI interrupt function is used to monitor the amount of
elapsed time since the initiation of the message transmission. Following this, each time an RTI interrupt
occurs, the RTI interrupt service routine will increment a counter stored in MCU RAM location "rticnt".
When the message is successfully transmitted, a transmission successful (TXMS) interrupt of the CPU will
be generated. When this occurs, the software will then disable the RTI interrupt, clear the RTI counter in
MCU RAM location "rticnt", and write $00 to the MTCR, clearing the interrupt. Following this, the MDLC
module will be ready for another message transmission. For an outline of the TXMS interrupt service
routine, refer to the transmit interrupt portion of
Figure 7b MDLC Interrupt Service Routine (concluded)
.
However, if the transmission successful (TXMS) interrupt does not occur before 8 RTI interrupts have been
counted, the transmission will be aborted. This gives the MDLC module approximately 30 ms to
successfully complete the transmission of a message. Due to the uncertainty of when the RTI interrupt is
enabled, the time allowed for the transmission to complete will vary between 7 and 8 RTI interrupts, or
between approximately 27 ms and 31 ms. This time period can easily be adjusted by the user by
increasing or decreasing the maximum RTI count in the RTI interrupt service routine. Also, if so desired,
the user can easily initiate another transmission attempt when the RTI counter reaches 8, rather than
simply aborting the transmission. Refer to
Figure 6 Real Time Interrupt Service Routine
for an outline of
the RTI interrupt handling sequence.
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