參數(shù)資料
型號： MC68HC705L16
廠商： 飛思卡爾半導體(中國)有限公司
英文描述： Microcontrollers
中文描述： 微控制器
文件頁數(shù)： 100/146頁
文件大?。?/td> 772K
代理商： MC68HC705L16
LCD Driver
MC68HC05L16 MC68HC705L16 Data Sheet, Rev. 4.1
100
Freescale Semiconductor
10.5 LCD Control Register
LCDE — LCD Output Enable
The LCDE bit enables all BP and FP outputs. (This bit does not affect PEH, PEL, or PDH bits.) This
bit is cleared on reset.
0 = All dedicated FP pins output highest (V
DD
) level; BP and FP pins are shared with an output port
data.
1 = All BP and FP pins output LCD waveforms.
DUTY1 and DUTY0 — LCD Duty Select
The DUTY1 and DUTY0 bits select the duty of the LCD driver. The number of BP pins is related to this
duty selection. The unused BP pin is used as a port D pin. Default duty is 1/4 duty. These bits are
cleared on reset. See
Table 10-1
.
Bit 4 — Reserved
This bit is not used and always reads as logic 0.
PEH — Select Port E (H)
The PEH bit enables the upper four bits of port E instead of LCD drivers. This bit is cleared on reset.
See
10.4 Frontplane Driver and Port Selection
.
0 = FP27–FP30 selected
1 = PE7–PE4 selected
PEL — Select Port E (L)
The PEL bit enables the lower four bits of port E instead of LCD drivers. This bit is cleared on reset.
See
10.4 Frontplane Driver and Port Selection
.
0 = FP31–FP34 selected
1 = PE3–PE0 selected
PDH — Select Port D (H)
The PDH bit enables the upper four bits of port D instead of LCD drivers. This bit is cleared on reset.
See
10.4 Frontplane Driver and Port Selection
.
0 = FP35–FP38 selected
1 = PD7–PD4 selected
Bit 0 — Reserved
This bit is not used and is always read as logic 0.
Address:
$0020
Bit 7
6
5
4
3
2
1
Bit 0
Read:
LCDE
DUTY1
DUTY0
0
PEH
PEL
PDH
0
Write:
Reset:
0
0
0
0
0
0
0
0
Figure 10-5. LCD Control Register (LCDCR)
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