參數(shù)資料
型號： MC68HC705K1
廠商： 飛思卡爾半導體(中國)有限公司
英文描述： HCMOS Microcontroller Unit
中文描述： HCMOS微控制器
文件頁數(shù)： 66/140頁
文件大?。?/td> 803K
代理商： MC68HC705K1
Technical Data
MC68HC705K1 — Rev. 2.0
Parallel Input/Output (I/O)
For More Information On This Product,
Go to: www.freescale.com
Parallel Input/Output (I/O)
7.4.3 Pulldown Register A
Programming the SWPDI bit in the mask option register to a logic 0
enables the port A and port B pulldown devices. The port A pulldown
devices sink approximately 100
μ
A and are under the control of the
PDIA7–PDIA0 bits in pulldown register A (PDRA).
Clearing the PDIA7–PDIA0 bits turns on the pulldown devices of the port
A pins that are configured as inputs. A pulldown device can be turned on
only when its pin is an input. When SWPDI is a logic 0, reset initializes
all port A pins as inputs with pulldown devices turned on.
Programming the SWPDI bit to a logic 1 disables the port A and port B
pulldown devices. Reset initializes all port A pins as inputs with pulldown
devices disabled when the SWPDI bit is programmed to a logic 1.
PDIA7–PDIA0 — Port A Pulldown Inhibit Bits 7–0
Writing logic 0s to these write-only bits turns on the port A pulldown
devices. Reading pulldown register A returns undefined data. Reset
clears bits PDIA7–PDIA0.
1 = Corresponding port A pin pulldown device turned off
0 = Corresponding port A pin pulldown device turned on
NOTE:
Avoid a floating port A input by clearing its pulldown register bit before
changing its DDRA bit from logic 1 to logic 0.
Do not use read-modify-write instructions on pulldown register A.
Address:
$0010
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
PDIA7
PDIA6
PDIA5
PDIA4
PDIA3
PDIA2
PDIA1
PDIA0
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 7-3. Pulldown Register A (PDRA)
F
Freescale Semiconductor, Inc.
n
.
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